Document Outline
- Chapter 1 About This Manual
- Chapter 2 System Architecture Overview
- Chapter 3 Protected-Mode Memory Management
- Chapter 4 Paging
- Chapter 5 Protection
- Chapter 6 Interrupt and Exception Handling
- Chapter 7 Task Management
- Chapter 8 Multiple-Processor Management
- Chapter 9 Processor Management and Initialization
- Chapter 10 Advanced Programmable Interrupt Controller (APIC)
- Chapter 11 Memory Cache Control
- Chapter 12 Intel® MMX™ Technology System Programming
- Chapter 13 System Programming for Instruction Set Extensions and Processor Extended States
- Chapter 14 Power and Thermal Management
- Chapter 15 Machine-Check Architecture
- Chapter 16 Interpreting Machine-Check Error Codes
- Chapter 17 Debug, Branch Profile, TSC, and Resource Monitoring Features
- 17.1 Overview of Debug Support Facilities
- 17.2 Debug Registers
- 17.3 Debug Exceptions
- 17.4 Last Branch, Interrupt, and Exception Recording Overview
- 17.5 Last Branch, Interrupt, and Exception Recording (Intel® Core™ 2 Duo and Intel® Atom™ Processors)
- 17.6 Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Goldmont Microarchitecture
- 17.7 Last Branch, Interrupt, and Exception Recording for Processors based on Intel® Microarchitecture code name Nehalem
- 17.8 Last Branch, Interrupt, and Exception Recording for Processors based on Intel® Microarchitecture code name Sandy Bridge
- 17.9 Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Haswell Microarchitecture
- 17.10 Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture
- 17.11 Last Branch, Interrupt, and Exception Recording (Processors based on Intel NetBurst® Microarchitecture)
- 17.12 Last Branch, Interrupt, and Exception Recording (Intel® Core™ Solo and Intel® Core™ Duo Processors)
- 17.13 Last Branch, Interrupt, and Exception Recording (Pentium M Processors)
- 17.14 Last Branch, Interrupt, and Exception Recording (P6 Family Processors)
- 17.15 Time-Stamp Counter
- 17.16 Intel® Resource Director Technology (Intel® RDT) Monitoring Features
- 17.17 Intel® Resource Director Technology (Intel® RDT) Allocation Features
- Chapter 18 Performance Monitoring
- Chapter 19 Performance-Monitoring Events
- Chapter 20 8086 Emulation
- Chapter 21 Mixing 16-Bit and 32-Bit Code
- Chapter 22 Architecture Compatibility
- Chapter 23 Introduction to Virtual Machine Extensions
- Chapter 24 Virtual Machine Control Structures
- Chapter 25 VMX Non-Root Operation
- Chapter 26 VM Entries
- Chapter 27 VM Exits
- Chapter 28 VMX Support for Address Translation
- Chapter 29 APIC Virtualization and Virtual Interrupts
- Chapter 30 VMX Instruction Reference
- Chapter 31 Virtual-Machine Monitor Programming Considerations
- Chapter 32 Virtualization of System Resources
- Chapter 33 Handling Boundary Conditions in a Virtual Machine Monitor
- Chapter 34 System Management Mode
- Chapter 35 Model-Specific Registers (MSRs)
- Chapter 36 Intel® Processor Trace
- Chapter 37 Introduction to Intel® Software Guard Extensions
- Chapter 38 Enclave Access Control and Data Structures
- Chapter 39 Enclave Operation
- Chapter 40 Enclave Exiting Events
- Chapter 41 SGX Instruction References
- Chapter 42 Intel® SGX Interactions with IA32 and Intel® 64 Architecture
- Chapter 43 Enclave Code Debug and Profiling
- Appendix A VMX Capability Reporting Facility
- Appendix B Field Encoding in VMCS
- Appendix C VMX Basic Exit Reasons