24-8 Vol. 3C
VIRTUAL MACHINE CONTROL STRUCTURES
See Chapter 29 for more information on the use of this field.
•
PML index (16 bits). This field is supported only on processors that support the 1-setting of the “enable PML”
VM-execution control. It contains the logical index of the next entry in the page-modification log. Because the
page-modification log comprises 512 entries, the PML index is typically a value in the range 0–511. Details of
the page-modification log and use of the PML index are given in Section 28.2.5.
24.5 HOST-STATE
AREA
This section describes fields contained in the host-state area of the VMCS. As noted earlier, processor state is
loaded from these fields on every VM exit (see Section 27.5).
All fields in the host-state area correspond to processor registers:
•
CR0, CR3, and CR4 (64 bits each; 32 bits on processors that do not support Intel 64 architecture).
•
RSP and RIP (64 bits each; 32 bits on processors that do not support Intel 64 architecture).
•
Selector fields (16 bits each) for the segment registers CS, SS, DS, ES, FS, GS, and TR. There is no field in the
host-state area for the LDTR selector.
•
Base-address fields for FS, GS, TR, GDTR, and IDTR (64 bits each; 32 bits on processors that do not support
Intel 64 architecture).
•
The following MSRs:
— IA32_SYSENTER_CS (32 bits)
— IA32_SYSENTER_ESP and IA32_SYSENTER_EIP (64 bits; 32 bits on processors that do not support Intel 64
architecture).
— IA32_PERF_GLOBAL_CTRL (64 bits). This field is supported only on processors that support the 1-setting of
the “load IA32_PERF_GLOBAL_CTRL” VM-exit control.
— IA32_PAT (64 bits). This field is supported only on processors that support the 1-setting of the “load
IA32_PAT” VM-exit control.
— IA32_EFER (64 bits). This field is supported only on processors that support the 1-setting of the “load
IA32_EFER” VM-exit control.
In addition to the state identified here, some processor state components are loaded with fixed values on every
VM exit; there are no fields corresponding to these components in the host-state area. See Section 27.5 for details
of how state is loaded on VM exits.
24.6
VM-EXECUTION CONTROL FIELDS
The VM-execution control fields govern VMX non-root operation. These are described in Section 24.6.1 through
Section 24.6.8.
24.6.1
Pin-Based VM-Execution Controls
The pin-based VM-execution controls constitute a 32-bit vector that governs the handling of asynchronous events
(for example: interrupts).
1
Table 24-5 lists the controls. See Chapter 27 for how these controls affect processor
behavior in VMX non-root operation.
1. Some asynchronous events cause VM exits regardless of the settings of the pin-based VM-execution controls (see Section 25.2).