Vol. 3C 29-3

APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS

29.1.4 EOI 

Virtualization

The processor performs EOI virtualization in response to the following operations: (1) virtualization of a write to 
offset 0B0H on the APIC-access page; and (2) virtualization of the WRMSR instruction with ECX = 80BH. See 
Section 29.4.3 and Section 29.5 for details of when EOI virtualization is performed. EOI virtualization occurs only 
if the “virtual-interrupt delivery” VM-execution control is 1.
EOI virtualization uses and updates the guest interrupt status (specifically, SVI; see Section 24.4.2). The following 
pseudocode details the behavior of EOI virtualization:

Vector ← SVI;

VISR[Vector] ← 0; (see Section 29.1.1 for definition of VISR)

IF any bits set in VISR

THEN SVI ← highest index of bit set in VISR

ELSE SVI ← 0;

FI;
perform PPR virtualiation (see Section 29.1.3);
IF EOI_exit_bitmap[Vector] = 1 (see Section 24.6.8 for definition of EOI_exit_bitmap)

THEN cause EOI-induced VM exit with Vector as exit qualification;
ELSE evaluate pending virtual interrupts; (see Section 29.2.1)

FI;

Any VM exit caused by EOI virtualization is trap-like: the instruction causing EOI virtualization completes before 
the VM exit occurs (for example, the value of CS:RIP saved in the guest-state area of the VMCS references the next 
instruction).

29.1.5 Self-IPI 

Virtualization

The processor performs self-IPI virtualization in response to the following operations: (1) virtualization of a 
write to offset 300H on the APIC-access page; and (2) virtualization of the WRMSR instruction with ECX = 83FH. 
See Section 29.4.3 and Section 29.5 for details of when self-IPI virtualization is performed. Self-IPI virtualization 
occurs only if the “virtual-interrupt delivery” VM-execution control is 1.
Each operation that leads to self-IPI virtualization provides an 8-bit vector (see Section 29.4.3 and Section 29.5). 
Self-IPI virtualization updates the guest interrupt status (specifically, RVI; see Section 24.4.2). The following 
pseudocode details the behavior of self-IPI virtualization:

VIRR[Vector] ← 1; (see Section 29.1.1 for definition of VIRR)

RVI ← max{RVI,Vector};

evaluate pending virtual interrupts; (see Section 29.2.1)

29.2 

EVALUATION AND DELIVERY OF VIRTUAL INTERRUPTS

If the “virtual-interrupt delivery” VM-execution control is 1, certain actions in VMX non-root operation or during 
VM entry cause the processor to evaluate and deliver virtual interrupts.
Evaluation of virtual interrupts is triggered by certain actions change the state of the virtual-APIC page and is 
described in Section 29.2.1. This evaluation may result in recognition of a virtual interrupt. Once a virtual interrupt 
is recognized, the processor may deliver it within VMX non-root operation without a VM exit. Virtual-interrupt 
delivery is described in Section 29.2.2.

29.2.1 

Evaluation of Pending Virtual Interrupts

If the “virtual-interrupt delivery” VM-execution control is 1, certain actions cause a logical processor to evaluate 
pending virtual interrupts.
The following actions cause the evaluation of pending virtual interrupts: VM entry; TPR virtualization; EOI virtual-
ization; self-IPI virtualization; and posted-interrupt processing. See Section 26.3.2.5, Section 29.1.2, Section