Vol. 3D A-5

VMX CAPABILITY REPORTING FACILITY

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Bits 63:32 indicate the allowed 1-settings of these controls. VM entry allows control X to be 1 if bit 32+X in the 
MSR is set to 1; if bit 32+X in the MSR is cleared to 0, VM entry fails if control X is 1.

It is necessary for software to consult only one of the capability MSRs to determine the allowed settings of the 
VM-exit controls:

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If bit 55 in the IA32_VMX_BASIC MSR is read as 0, all information about the allowed settings of the VM-exit 
controls is contained in the IA32_VMX_EXIT_CTLS MSR. (The IA32_VMX_TRUE_EXIT_CTLS MSR is not 
supported.)

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If bit 55 in the IA32_VMX_BASIC MSR is read as 1, all information about the allowed settings of the VM-exit 
controls is contained in the IA32_VMX_TRUE_EXIT_CTLS MSR. Assuming that software knows that the default1 
class of VM-exit controls contains bits 0–8, 10, 11, 13, 14, 16, and 17, there is no need for software to consult 
the IA32_VMX_EXIT_CTLS MSR.

A.5 VM-ENTRY 

CONTROLS

The IA32_VMX_ENTRY_CTLS MSR (index 484H) reports on the allowed settings of most of the VM-entry controls 
(see Section 24.8.1):

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Bits 31:0 indicate the allowed 0-settings of these controls. VM entry allows control X (bit X of the VM-entry 
controls) to be 0 if bit X in the MSR is cleared to 0; if bit X in the MSR is set to 1, VM entry fails if control X is 0.
Exceptions are made for the VM-entry controls in the default1 class (see Appendix A.2). These are bits 0–8 and 
12; the corresponding bits of the IA32_VMX_ENTRY_CTLS MSR are always read as 1. The treatment of these 
controls by VM entry is determined by bit 55 in the IA32_VMX_BASIC MSR:
— If bit 55 in the IA32_VMX_BASIC MSR is read as 0, VM entry fails if any VM-entry control in the default1 

class is 0.

— If bit 55 in the IA32_VMX_BASIC MSR is read as 1, the IA32_VMX_TRUE_ENTRY_CTLS MSR (see below) 

reports which of the VM-entry controls in the default1 class can be 0 on VM entry.

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Bits 63:32 indicate the allowed 1-settings of these controls. VM entry fails if bit X is 1 in the VM-entry controls 
and bit 32+X is 0 in this MSR.

If bit 55 in the IA32_VMX_BASIC MSR is read as 1, the IA32_VMX_TRUE_ENTRY_CTLS MSR (index 490H) reports 
on the allowed settings of all of the VM-entry controls:

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Bits 31:0 indicate the allowed 0-settings of these controls. VM entry allows control X to be 0 if bit X in the MSR 
is cleared to 0; if bit X in the MSR is set to 1, VM entry fails if control X is 0. There are no exceptions.

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Bits 63:32 indicate the allowed 1-settings of these controls. VM entry allows control 32+X to be 1 if bit X in the 
MSR is set to 1; if bit 32+X in the MSR is cleared to 0, VM entry fails if control X is 1.

It is necessary for software to consult only one of the capability MSRs to determine the allowed settings of the 
VM-entry controls:

•

If bit 55 in the IA32_VMX_BASIC MSR is read as 0, all information about the allowed settings of the VM-entry 
controls is contained in the IA32_VMX_ENTRY_CTLS MSR. (The IA32_VMX_TRUE_ENTRY_CTLS MSR is not 
supported.)

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If bit 55 in the IA32_VMX_BASIC MSR is read as 1, all information about the allowed settings of the VM-entry 
controls is contained in the IA32_VMX_TRUE_ENTRY_CTLS MSR. Assuming that software knows that the 
default1 class of VM-entry controls contains bits 0–8 and 12, there is no need for software to consult the 
IA32_VMX_ENTRY_CTLS MSR.

A.6 MISCELLANEOUS 

DATA

The IA32_VMX_MISC MSR (index 485H) consists of the following fields:

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Bits 4:0 report a value X that specifies the relationship between the rate of the VMX-preemption timer and that 
of the timestamp counter (TSC). Specifically, the VMX-preemption timer (if it is active) counts down by 1 every 
time bit X in the TSC changes due to a TSC increment.