Vol. 3A 10-45

ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)

A destination ID value of FFFF_FFFFH is used for broadcast of interrupts in both logical destination and physical 
destination modes.

10.12.10 Determining IPI Destination in x2APIC Mode

10.12.10.1  Logical Destination Mode in x2APIC Mode

In x2APIC mode, the Logical Destination Register (LDR) is increased to 32 bits wide. It is a read-only register to 
system software. This 32-bit value is referred to as “logical x2APIC ID”. System software accesses this register via 
the RDMSR instruction reading the MSR at address 80DH. Figure 10-29 provides the layout of the Logical Destina-
tion Register in x2APIC mode. 

In the xAPIC mode, the Destination Format Register (DFR) through MMIO interface determines the choice of a flat 
logical mode or a clustered logical mode. Flat logical mode is not supported in the x2APIC mode. Hence the Desti-
nation Format Register (DFR) is eliminated in x2APIC mode. 
The 32-bit logical x2APIC ID field of LDR is partitioned into two sub-fields:

•

Cluster ID (LDR[31:16]): is the address of the destination cluster

•

Logical ID (LDR[15:0]): defines a logical ID of the individual local x2APIC within the cluster specified by 
LDR[31:16]. 

This layout enables 2^16-1 clusters each with up to 16 unique logical IDs - effectively providing an addressability 
of ((2^20) - 16) processors in logical destination mode. 
It is likely that processor implementations may choose to support less than 16 bits of the cluster ID or less than 16-
bits of the Logical ID in the Logical Destination Register. However system software should be agnostic to the 
number of bits implemented in the cluster ID and logical ID sub-fields. The x2APIC hardware initialization will 
ensure that the appropriately initialized logical x2APIC IDs are available to system software and reads of non-
implemented bits return zero. This is a read-only register that software must read to determine the logical x2APIC 
ID of the processor. Specifically, software can apply a 16-bit mask to the lowest 16 bits of the logical x2APIC ID to 
identify the logical address of a processor within a cluster without needing to know the number of implemented bits 
in cluster ID and Logical ID sub-fields. Similarly, software can create a message destination address for cluster 
model, by bit-Oring the Logical X2APIC ID (31:0) of processors that have matching Cluster ID(31:16).
To enable cluster ID assignment in a fashion that matches the system topology characteristics and to enable effi-
cient routing of logical mode lowest priority device interrupts in link based platform interconnects, the LDR are 
initialized by hardware based on the value of x2APIC ID upon x2APIC state transitions. Details of this initialization 
are provided in Section 10.12.10.2. 

10.12.10.2  Deriving Logical x2APIC ID from the Local x2APIC ID

In x2APIC mode, the 32-bit logical x2APIC ID, which can be read from LDR, is derived from the 32-bit local x2APIC 
ID. Specifically, the 16-bit logical ID sub-field is derived by shifting 1 by the lowest 4 bits of the x2APIC ID, i.e. 
Logical ID = 1 « x2APIC ID[3:0]. The remaining bits of the x2APIC ID then form the cluster ID portion of the logical 
x2APIC ID: 

Figure 10-29.  Logical Destination Register in x2APIC Mode

MSR Address: 80DH

31

    

0

Logical x2APIC ID