Vol. 3B 19-1

CHAPTER 19

PERFORMANCE-MONITORING EVENTS

This chapter lists the performance-monitoring events that can be monitored with the Intel 64 or IA-32 processors. 
The ability to monitor performance events and the events that can be monitored in these processors are mostly 
model-specific, except for architectural performance events, described in Section 19.1. 
Non-architectural performance events (i.e. model-specific events) are listed for each generation of microarchitec-
ture:

•

Section 19.2 - Processors based on Skylake microarchitecture

•

Section 19.3 - Processors based on Broadwell microarchitecture

•

Section 19.4 - Processors based on Haswell microarchitecture

•

Section 19.4.1 - Processors based on Haswell-E microarchitecture 

•

Section 19.5 - Processors based on Ivy Bridge microarchitecture

•

Section 19.5.1 - Processors based on Ivy Bridge-E microarchitecture

•

Section 19.6 - Processors based on Sandy Bridge microarchitecture 

•

Section 19.7 - Processors based on Intel

®

 microarchitecture code name Nehalem

•

Section 19.8 - Processors based on Intel

®

 microarchitecture code name Westmere

•

Section 19.9 - Processors based on Enhanced Intel

®

 Core™ microarchitecture

•

Section 19.10 - Processors based on Intel

®

 Core™ microarchitecture

•

Section 19.11 - Processors based on the Goldmont microarchitecture

•

Section 19.12 - Processors based on the Silvermont microarchitecture

•

Section 19.12.1 - Processors based on the Airmont microarchitecture

•

Section 19.13 - 45 nm and 32 nm Intel

®

 Atom™ Processors

•

Section 19.14 - Intel

®

 Core™ Solo and Intel

®

 Core™ Duo processors

•

Section 19.15 - Processors based on Intel NetBurst

®

 microarchitecture

•

Section 19.16 - Pentium

®

 M family processors

•

Section 19.17 - P6 family processors

•

Section 19.18 - Pentium

®

 processors

NOTE

These performance-monitoring events are intended to be used as guides for performance tuning. 
The counter values reported by the performance-monitoring events are approximate and believed 
to be useful as relative guides for tuning software. Known discrepancies are documented where 
applicable. 
All performance event encodings not documented in the appropriate tables for the given processor 
are considered reserved, and their use will result in undefined counter updates with associated 
overflow actions.
The event tables listed this chapter provide information for tool developers to support architectural 
and non-architectural performance monitoring events. The tables are up to date at processor 
launch, but are subject to changes. The most up to date event tables and additional details of 
performance event implementation for end-user (including additional details beyond event 
code/umask) can found at the “perfmon” repository provided by The Intel Open Source Technology 
Center (https://download.01.org/perfmon/).