Vol. 3B 15-5

MACHINE-CHECK ARCHITECTURE

15.3.1.4   IA32_MCG_EXT_CTL MSR

The IA32_MCG_EXT_CTL MSR is present if the capability flag MCG_LMCE_P is set in the IA32_MCG_CAP MSR.
IA32_MCG_EXT_CTL.LMCE_EN (bit 0) allows the processor to signal some MCEs to only a single logical processor 
in the system.
If MCG_LMCE_P is not set in IA32_MCG_CAP, or platform software has not enabled LMCE by setting 
IA32_FEATURE_CONTROL.LMCE_ON (bit 20), any attempt to write or read IA32_MCG_EXT_CTL will result in #GP. 
The IA32_MCG_EXT_CTL MSR is cleared on RESET.
Figure 15-4 shows the layout of the IA32_MCG_EXT_CTL register

where

•

LMCE_EN (local machine check exception enable) flag, bit 0 - System software sets this to allow 
hardware to signal some MCEs to only a single logical processor. System software can set LMCE_EN only if the 
platform software has configured IA32_FEATURE_CONTROL as described in Section 15.3.1.5. 

15.3.1.5   Enabling Local Machine Check

The intended usage of LMCE requires proper configuration by both platform software and system software. Plat-
form software can turn LMCE on by setting bit 20 (LMCE_ON) in IA32_FEATURE_CONTROL MSR (MSR address 
3AH). 
System software must ensure that both IA32_FEATURE_CONTROL.Lock (bit 0)and 
IA32_FEATURE_CONTROL.LMCE_ON (bit 20) are set before attempting to set IA32_MCG_EXT_CTL.LMCE_EN (bit 
0). When system software has enabled LMCE, then hardware will determine if a particular error can be delivered 
only to a single logical processor. Software should make no assumptions about the type of error that hardware can 
choose to deliver as LMCE. The severity and override rules stay the same as described in Table 15-7 to determine 
the recovery actions. 

15.3.2 

Error-Reporting Register Banks

Each error-reporting register bank can contain the IA32_MCi_CTL, IA32_MCi_STATUS, IA32_MCi_ADDR, and 
IA32_MCi_MISC MSRs. The number of reporting banks is indicated by bits [7:0] of IA32_MCG_CAP MSR (address 
0179H). The first error-reporting register (IA32_MC0_CTL) always starts at address 400H. 
See Chapter 35, “Model-Specific Registers (MSRs),” for addresses of the error-reporting registers in the Pentium 4, 
Intel Atom, and Intel Xeon processors; and for addresses of the error-reporting registers P6 family processors. 

15.3.2.1   IA32_MC

i

_CTL MSRs

The IA32_MCi_CTL MSR controls signaling of #MC for errors produced by a particular hardware unit (or group of 
hardware units). Each of the 64 flags (EEj) represents a potential error. Setting an EEj flag enables signaling #MC 
of the associated error and clearing it disables signaling of the error. Error logging happens regardless of the 
setting of these bits. The processor drops writes to bits that are not implemented. Figure 15-5 shows the bit fields 
of IA32_MCi_CTL.

Figure 15-4.  IA32_MCG_EXT_CTL Register

63

0

Reserved

1

LMCE_EN - system software control to enable/disable LMCE