Vol. 3B 14-1

CHAPTER 14

POWER AND THERMAL MANAGEMENT

This chapter describes facilities of Intel 64 and IA-32 architecture used for power management and thermal moni-
toring.

14.1 ENHANCED 

INTEL 

SPEEDSTEP

®

 TECHNOLOGY

Enhanced Intel SpeedStep

®

 Technology was introduced in the Pentium M processor. The technology enables the 

management of processor power consumption via performance state transitions. These states are defined as 
discrete operating points associated with different voltages and frequencies. 
Enhanced Intel SpeedStep Technology differs from previous generations of Intel SpeedStep Technology in two 
ways:

•

Centralization of the control mechanism and software interface in the processor by using model-specific 
registers.

•

Reduced hardware overhead; this permits more frequent performance state transitions.

Previous generations of the Intel SpeedStep Technology require processors to be a deep sleep state, holding off bus 
master transfers for the duration of a performance state transition. Performance state transitions under the 
Enhanced Intel SpeedStep Technology are discrete transitions to a new target frequency.
Support is indicated by CPUID, using ECX feature bit 07. Enhanced Intel SpeedStep Technology is enabled by 
setting IA32_MISC_ENABLE MSR, bit 16. On reset, bit 16 of IA32_MISC_ENABLE MSR is cleared. 

14.1.1 

Software Interface For Initiating Performance State Transitions

State transitions are initiated by writing a 16-bit value to the IA32_PERF_CTL register, see Figure 14-2. If a transi-
tion is already in progress, transition to a new value will subsequently take effect. 
Reads of IA32_PERF_CTL determine the last targeted operating point. The current operating point can be read from 
IA32_PERF_STATUS. IA32_PERF_STATUS is updated dynamically.
The 16-bit encoding that defines valid operating points is model-specific. Applications and performance tools are 
not expected to use either IA32_PERF_CTL or IA32_PERF_STATUS and should treat both as reserved. Performance 
monitoring tools can access model-specific events and report the occurrences of state transitions.

14.2 P-STATE 

HARDWARE 

COORDINATION

The Advanced Configuration and Power Interface (ACPI) defines performance states (P-states) that are used to 
facilitate system software’s ability to manage processor power consumption. Different P-states correspond to 
different performance levels that are applied while the processor is actively executing instructions. Enhanced Intel 
SpeedStep Technology supports P-states by providing software interfaces that control the operating frequency and 
voltage of a processor. 
With multiple processor cores residing in the same physical package, hardware dependencies may exist for a 
subset of logical processors on a platform. These dependencies may impose requirements that impact the coordi-
nation of P-state transitions. As a result, multi-core processors may require an OS to provide additional software 
support for coordinating P-state transitions for those subsets of logical processors.
ACPI firmware can choose to expose P-states as dependent and hardware-coordinated to OS power management 
(OSPM) policy. To support OSPMs, multi-core processors must have additional built-in support for P-state hardware 
coordination and feedback.
Intel 64 and IA-32 processors with dependent P-states amongst a subset of logical processors permit hardware 
coordination of P-states and provide a hardware-coordination feedback mechanism using IA32_MPERF MSR and