27-12 Vol. 3C

VM EXITS

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An EPT violation, EPT misconfiguration, or page-modification log-full event that occurs during event delivery.

These fields are used for VM exits that occur during delivery of events injected as part of VM entry (see Section 
26.5.1.2).
A VM exit is not considered to occur during event delivery in any of the following circumstances:

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The original event causes the VM exit directly (for example, because the original event is a non-maskable 
interrupt (NMI) and the “NMI exiting” VM-execution control is 1).

•

The original event results in a double-fault exception that causes the VM exit directly.

•

The VM exit occurred as a result of fetching the first instruction of the handler invoked by the event delivery.

•

The VM exit is caused by a triple fault.

The following items detail the use of these fields:

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IDT-vectoring information (format given in Table 24-16). The following items detail how this field is established 
for VM exits that occur during event delivery:
— If the VM exit occurred during delivery of an exception, bits 7:0 receive the exception vector (at most 31). 

If the VM exit occurred during delivery of an NMI, bits 7:0 are set to 2. If the VM exit occurred during 
delivery of an external interrupt, bits 7:0 receive the vector.

— Bits 10:8 are set to indicate the type of event that was being delivered when the VM exit occurred: 0 

(external interrupt), 2 (non-maskable interrupt), 3 (hardware exception), 4 (software interrupt), 5 
(privileged software interrupt), or 6 (software exception).
Hardware exceptions comprise all exceptions except breakpoint exceptions (#BP; generated by INT3) and 
overflow exceptions (#OF; generated by INTO); these are software exceptions. (A #BP that occurs in 
enclave mode is considered a hardware exception.) BOUND-range exceeded exceptions (#BR; generated 
by BOUND) and invalid opcode exceptions (#UD) generated by UD2 are hardware exceptions.
Bits 10:8 may indicate privileged software interrupt if such an event was injected as part of VM entry.

— Bit 11 is set to 1 if the VM exit occurred during delivery of a hardware exception that would have delivered 

an error code on the stack. This bit is always 0 if the VM exit occurred while the logical processor was in 
real-address mode (CR0.PE=0).

1

 If bit 11 is set to 1, the error code is placed in the IDT-vectoring error 

code (see below).

— Bit 12 is undefined.
— Bits 30:13 are always set to 0.
— Bit 31 is always set to 1.
For other VM exits, the field is marked invalid (by clearing bit 31) and the remainder of the field is undefined.

•

IDT-vectoring error code. 
— For VM exits that set both bit 31 (valid) and bit 11 (error code valid) in the IDT-vectoring information field, 

this field receives the error code that would have been pushed on the stack by the event that was being 
delivered through the IDT at the time of the VM exit. The EXT bit is set in this field when it would be set 
normally.

— For other VM exits, the value of this field is undefined.

27.2.4 

Information for VM Exits Due to Instruction Execution

Section 24.9.4 defined fields containing information for VM exits that occur due to instruction execution. (The VM-
exit instruction length is also used for VM exits that occur during the delivery of a software interrupt or software 
exception.) The following items detail their use.

•

VM-exit instruction length. This field is used in the following cases:

1. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PE must be 1 in VMX operation, a logical processor cannot be in real-

address mode unless the “unrestricted guest” VM-execution control and bit 31 of the primary processor-based VM-execution con-

trols are both 1.