Vol. 3A 6-3

INTERRUPT AND EXCEPTION HANDLING

The processor’s local APIC is normally connected to a system-based I/O APIC. Here, external interrupts received at 
the I/O APIC’s pins can be directed to the local APIC through the system bus (Pentium 4, Intel Core Duo, Intel Core 
2, Intel

®

 Atom™, and Intel Xeon processors) or the APIC serial bus (P6 family and Pentium processors). The I/O 

APIC determines the vector number of the interrupt and sends this number to the local APIC. When a system 
contains multiple processors, processors can also send interrupts to one another by means of the system bus 
(Pentium 4, Intel Core Duo, Intel Core 2, Intel Atom, and Intel Xeon processors) or the APIC serial bus (P6 family 
and Pentium processors). 
The LINT[1:0] pins are not available on the Intel486 processor and earlier Pentium processors that do not contain 
an on-chip local APIC. These processors have dedicated NMI and INTR pins. With these processors, external inter-
rupts are typically generated by a system-based interrupt controller (8259A), with the interrupts being signaled 
through the INTR pin.
Note that several other pins on the processor can cause a processor interrupt to occur. However, these interrupts 
are not handled by the interrupt and exception mechanism described in this chapter. These pins include the 
RESET#, FLUSH#, STPCLK#, SMI#, R/S#, and INIT# pins. Whether they are included on a particular processor is 
implementation dependent. Pin functions are described in the data books for the individual processors. The SMI# 
pin is described in Chapter 34, “System Management Mode.”

6.3.2 

Maskable Hardware Interrupts

Any external interrupt that is delivered to the processor by means of the INTR pin or through the local APIC is called 
a maskable hardware interrupt. Maskable hardware interrupts that can be delivered through the INTR pin include 
all IA-32 architecture defined interrupt vectors from 0 through 255; those that can be delivered through the local 
APIC include interrupt vectors 16 through 255. 
The IF flag in the EFLAGS register permits all maskable hardware interrupts to be masked as a group (see Section 
6.8.1, “Masking Maskable Hardware Interrupts”). Note that when interrupts 0 through 15 are delivered through the 
local APIC, the APIC indicates the receipt of an illegal vector. 

15

—

(Intel reserved. Do not use.)

No

16

#MF

x87 FPU Floating-Point Error (Math 

Fault)

Fault

No

x87 FPU floating-point or WAIT/FWAIT 

instruction.

17

#AC

Alignment Check

Fault

Yes 

(Zero)

Any data reference in memory.

3

18

#MC

Machine Check

Abort

No

Error codes (if any) and source are model 

dependent.

4

19

#XM

SIMD Floating-Point Exception

Fault

No

SSE/SSE2/SSE3 floating-point 

instructions

5

20

#VE

Virtualization Exception

Fault

No

EPT violations

6

21-31

—

Intel reserved. Do not use.

32-255

—

User Defined (Non-reserved) 

Interrupts

Interrupt

External interrupt or INT n instruction.

NOTES:

1. The UD2 instruction was introduced in the Pentium Pro processor.
2. Processors after the Intel386 processor do not generate this exception.
3. This exception was introduced in the Intel486 processor.
4. This exception was introduced in the Pentium processor and enhanced in the P6 family processors.
5. This exception was introduced in the Pentium III processor.
6. This exception can occur only on processors that support the 1-setting of the “EPT-violation #VE” VM-execution control.

Table 6-1.  Protected-Mode Exceptions and Interrupts  (Contd.)