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Vol. 3A 8-33

MULTIPLE-PROCESSOR MANAGEMENT

cores or different physical packages. Either logical processor that has access to the microcode update facility can 
initiate an update. 
Each logical processor has its own BIOS signature MSR (IA32_BIOS_SIGN_ID at MSR address 8BH). When a logical 
processor performs an update for the physical processor, the IA32_BIOS_SIGN_ID MSRs for resident logical 
processors are updated with identical information. 
All microcode update steps during processor initialization should use the same update data on all cores in all phys-
ical packages of the same stepping. Any subsequent microcode update must apply consistent update data to all 
cores in all physical packages of the same stepping. If the processor detects an attempt to load an older microcode 
update when a newer microcode update had previously been loaded, it may reject the older update to stay with the 
newer update.

NOTE

Some processors (prior to the introduction of Intel 64 Architecture and based on Intel NetBurst 
microarchitecture) do not support simultaneous loading of microcode update to the sibling logical 
processors in the same core. All other processors support logical processors initiating an update 
simultaneously. Intel recommends a common approach that the microcode loader use the 
sequential technique described in Section 9.11.6.3.

8.9 PROGRAMMING 

CONSIDERATIONS 

FOR HARDWARE MULTI-THREADING 

CAPABLE PROCESSORS

In a multi-threading environment, there may be certain hardware resources that are physically shared at some 
level of the hardware topology. In the multi-processor systems, typically bus and memory sub-systems are physi-
cally shared between multiple sockets. Within a hardware multi-threading capable processors, certain resources 
are provided for each processor core, while other resources may be provided for each logical processors (see 
Section 8.7, “Intel

®

 Hyper-Threading Technology Architecture,” and Section 8.8, “Multi-Core Architecture”). 

From a software programming perspective, control transfer of processor operation is managed at the granularity of 
logical processor (operating systems dispatch a runnable task by allocating an available logical processor on the 
platform). To manage the topology of shared resources in a multi-threading environment, it may be useful for soft-
ware to understand and manage resources that are shared by more than one logical processors.

8.9.1 

Hierarchical Mapping of Shared Resources

The APIC_ID value associated with each logical processor in a multi-processor system is unique (see Section 8.6, 
“Detecting Hardware Multi-Threading Support and Topology”). 
This 8-bit or 32-bit value can be decomposed into 
sub-fields, where each sub-field corresponds a hierarchical level of the topological mapping of hardware resources. 
The decomposition of an APIC_ID may consist of several sub fields representing the topology within a physical 
processor package, the higher-order bits of an APIC ID may also be used by cluster vendors to represent the 
topology of cluster nodes of each coherent multiprocessor systems. If the processor does not support CPUID leaf 
0BH, the 8-bit initial APIC ID can represent 4 levels of hierarchy:

Cluster — Some multi-threading environments consists of multiple clusters of multi-processor systems. The 
CLUSTER_ID sub-field is usually supported by vendor firmware to distinguish different clusters. For non-
clustered systems, CLUSTER_ID is usually 0 and system topology is reduced to three levels of hierarchy.

Package — A multi-processor system consists of two or more sockets, each mates with a physical processor 
package. The PACKAGE_ID sub-field distinguishes different physical packages within a cluster.

Core — A physical processor package consists of one or more processor cores. The CORE_ID sub-field distin-
guishes processor cores in a package. For a single-core processor, the width of this bit field is 0.

SMT — A processor core provides one or more logical processors sharing execution resources. The SMT_ID 
sub-field distinguishes logical processors in a core. The width of this bit field is non-zero if a processor core 
provides more than one logical processors.

SMT and CORE sub-fields are bit-wise contiguous in the APIC_ID field (see Figure 8-5).