34-30 Vol. 3C

SYSTEM MANAGEMENT MODE

The interface to enable SMM handler code access check resides in a per-package scope model-specific register 
MSR_SMM_FEATURE_CONTROL at address 4E0H. An attempt to access MSR_SMM_FEATURE_CONTROL outside of 
SMM will cause a #GP. Writes to MSR_SMM_FEATURE_CONTROL is further protected by configuration interface of 
MSR_SMM_MCA_CAP at address 17DH.
Details of the interface of MSR_SMM_FEATURE_CONTROL and MSR_SMM_MCA_CAP are described in Table 35-27.

34.17.2  SMI Delivery Delay Reporting 

Entry into the system management mode occurs at instruction boundary. In situations where a logical processor is 
executing an instruction involving a long flow of internal operations, servicing an SMI by that logical processor will 
be delayed. Delayed servicing of SMI of each logical processor due to executing long flows of internal operation in 
a physical processor can be queried via a package-scope register MSR_SMM_DELAYED at address 4E2H.
The interface to enable reporting of SMI delivery delay due to long internal flows resides in a per-package scope 
model-specific register MSR_SMM_DELAYED. An attempt to access MSR_SMM_DELAYED outside of SMM will cause 
a #GP. Availability to MSR_SMM_DELAYED is protected by configuration interface of MSR_SMM_MCA_CAP at 
address 17DH.
Details of the interface of MSR_SMM_DELAYED and MSR_SMM_MCA_CAP are described in Table 35-27.

34.17.3  Blocked SMI Reporting 

A logical processor may have entered into a state and blocked from servicing other interrupts (including SMI). 
Logical processors in a physical processor that are blocked in serving SMI can be queried in a package-scope 
register MSR_SMM_BLOCKED at address 4E3H. An attempt to access MSR_SMM_BLOCKED outside of SMM will 
cause a #GP.
Details of the interface of MSR_SMM_BLOCKED is described in Table 35-27.