Vol. 3C 34-15

SYSTEM MANAGEMENT MODE

In multiple-processor systems, initialization software must adjust the SMBASE value for each processor so that the 
SMRAM state save areas for each processor do not overlap. (For Pentium and Intel486 processors, the SMBASE 
values must be aligned on a 32-KByte boundary or the processor will enter shutdown state during the execution of 
a RSM instruction.)
If the SMBASE relocation flag in the SMM revision identifier field is set, it indicates the ability to relocate the 
SMBASE (see Section 34.9).

34.12 I/O 

INSTRUCTION 

RESTART

If the I/O instruction restart flag in the SMM revision identifier field is set (see Section 34.9), the I/O instruction 
restart mechanism is present on the processor. This mechanism allows an interrupted I/O instruction to be re-
executed upon returning from SMM mode. For example, if an I/O instruction is used to access a powered-down I/O 
device, a chip set supporting this device can intercept the access and respond by asserting SMI#. This action 
invokes the SMI handler to power-up the device. Upon returning from the SMI handler, the I/O instruction restart 
mechanism can be used to re-execute the I/O instruction that caused the SMI.
The I/O instruction restart field (at offset 7F00H in the SMM state-save area, see Figure 34-5) controls I/O instruc-
tion restart. When an RSM instruction is executed, if this field contains the value FFH, then the EIP register is modi-
fied to point to the I/O instruction that received the SMI request. The processor will then automatically re-execute 
the I/O instruction that the SMI trapped. (The processor saves the necessary machine state to insure that re-
execution of the instruction is handled coherently.)

If the I/O instruction restart field contains the value 00H when the RSM instruction is executed, then the processor 
begins program execution with the instruction following the I/O instruction. (When a repeat prefix is being used, 
the next instruction may be the next I/O instruction in the repeat loop.) Not re-executing the interrupted I/O 
instruction is the default behavior; the processor automatically initializes the I/O instruction restart field to 00H 
upon entering SMM. Table 34-8 summarizes the states of the I/O instruction restart field.

The I/O instruction restart mechanism does not indicate the cause of the SMI. It is the responsibility of the SMI 
handler to examine the state of the processor to determine the cause of the SMI and to determine if an I/O instruc-
tion was interrupted and should be restarted upon exiting SMM. If an SMI interrupt is signaled on a non-I/O 
instruction boundary, setting the I/O instruction restart field to FFH prior to executing the RSM instruction will likely 
result in a program error.

 

Figure 34-4.  SMBASE Relocation Field

 

Figure 34-5.  I/O Instruction Restart Field

Table 34-8.  I/O Instruction Restart Field Values

Value of Flag After 

Entry to SMM

Value of Flag When 

Exiting SMM

Action of Processor When Exiting SMM

00H
00H

00H
FFH

Does not re-execute trapped I/O instruction.
Re-executes trapped I/O instruction.

0

31

SMM Base

Register Offset
7EF8H

0

15

I/O Instruction Restart Field

Register Offset
7F00H