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PAGING

Because the G flag is used only in paging-structure entries that map a page, and because information from such 
entries is not cached in the paging-structure caches, the global-page feature does not affect the behavior of the 
paging-structure caches.
A logical processor may use a global TLB entry to translate a linear address, even if the TLB entry is associated with 
a PCID different from the current PCID.

4.10.3 Paging-Structure 

Caches

In addition to the TLBs, a processor may cache other information about the paging structures in memory.

4.10.3.1   Caches for Paging Structures

A processor may support any or all of the following paging-structure caches:

•

PML4 cache (IA-32e paging only). Each PML4-cache entry is referenced by a 9-bit value and is used for linear 
addresses for which bits 47:39 have that value. The entry contains information from the PML4E used to 
translate such linear addresses:
— The physical address from the PML4E (the address of the page-directory-pointer table).
— The value of the R/W flag of the PML4E.
— The value of the U/S flag of the PML4E.
— The value of the XD flag of the PML4E.
— The values of the PCD and PWT flags of the PML4E.
The following items detail how a processor may use the PML4 cache:
— If the processor has a PML4-cache entry for a linear address, it may use that entry when translating the 

linear address (instead of the PML4E in memory).

— The processor does not create a PML4-cache entry unless the P flag is 1 and all reserved bits are 0 in the 

PML4E in memory.

— The processor does not create a PML4-cache entry unless the accessed flag is 1 in the PML4E in memory; 

before caching a translation, the processor sets the accessed flag if it is not already 1.

— The processor may create a PML4-cache entry even if there are no translations for any linear address that 

might use that entry (e.g., because the P flags are 0 in all entries in the referenced page-directory-pointer 
table).

— If the processor creates a PML4-cache entry, the processor may retain it unmodified even if software subse-

quently modifies the corresponding PML4E in memory.

•

PDPTE cache (IA-32e paging only).

1

 Each PDPTE-cache entry is referenced by an 18-bit value and is used for 

linear addresses for which bits 47:30 have that value. The entry contains information from the PML4E and 
PDPTE used to translate such linear addresses:
— The physical address from the PDPTE (the address of the page directory). (No PDPTE-cache entry is created 

for a PDPTE that maps a 1-GByte page.)

— The logical-AND of the R/W flags in the PML4E and the PDPTE.
— The logical-AND of the U/S flags in the PML4E and the PDPTE.
— The logical-OR of the XD flags in the PML4E and the PDPTE.
— The values of the PCD and PWT flags of the PDPTE.
The following items detail how a processor may use the PDPTE cache:
— If the processor has a PDPTE-cache entry for a linear address, it may use that entry when translating the 

linear address (instead of the PML4E and the PDPTE in memory).

1. With PAE paging, the PDPTEs are stored in internal, non-architectural registers. The operation of these registers is described in Sec-

tion 4.4.1 and differs from that described here.