Vol. 3D 43-9

ENCLAVE CODE DEBUG AND PROFILING

the end of AEX. Consequently, fault-like events such as page faults, EPT faults, EPT mis-configuration, and 
accesses to APIC-access page detected on stores to the PEBS/BTS buffer are not reported, and generation of the 
PEBS and/or BTS record at the end of AEX is aborted (this may leave the buffers in a state where they have partial 
PEBS or BTS records). Trap-like events detected on stores to the PEBS/BTS buffer (such as debug traps) are 
pended until the next instruction boundary, where they are handled according to the architecturally defined 
priority. The processor continues the handling of the Enclave Exiting Event (SMI, NMI, interrupt, exception delivery, 
VM exit, etc.) after aborting the PEBS/BTS record generation. 

43.6.6.1   Other Interactions with Performance Monitoring

For opt-in entry, EENTER, ERESUME, EEXIT, and AEX are all treated as predicted far branches, and any counters 
that are counting such branches are incremented by 1 as a part of retirement of these instructions. Retirement of 
these instructions is also counted in any counters configured to count instructions retired.
For opt-out entry, execution inside an enclave is treated as a single predicted branch, and all branch-counting 
performance monitoring counters are incremented accordingly. Additionally, such execution is also counted as a 
single instruction, and all performance monitoring counters counting instructions are incremented accordingly.
Enclave entry does not affect any performance monitoring counters shared between cores.