27-20 Vol. 3C

VM EXITS

27.3 

SAVING GUEST STATE

Each field in the guest-state area of the VMCS (see Section 24.4) is written with the corresponding component of 
processor state. On processors that support Intel 64 architecture, the full values of each natural-width field (see 
Section 24.11.2) is saved regardless of the mode of the logical processor before and after the VM exit.
In general, the state saved is that which was in the logical processor at the time the VM exit commences. See 
Section 27.1 for a discussion of which architectural updates occur at that time.
Section 27.3.1 through Section 27.3.4 provide details for how certain components of processor state are saved. 
These sections reference VMCS fields that correspond to processor state. Unless otherwise stated, these references 
are to fields in the guest-state area.

27.3.1 

Saving Control Registers, Debug Registers, and MSRs

Contents of certain control registers, debug registers, and MSRs is saved as follows:

•

The contents of CR0, CR3, CR4, and the IA32_SYSENTER_CS, IA32_SYSENTER_ESP, and IA32_SYSENTER_EIP 
MSRs are saved into the corresponding fields. Bits 63:32 of the IA32_SYSENTER_CS MSR are not saved. On 
processors that do not support Intel 64 architecture, bits 63:32 of the IA32_SYSENTER_ESP and 
IA32_SYSENTER_EIP MSRs are not saved.

•

If the “save debug controls” VM-exit control is 1, the contents of DR7 and the IA32_DEBUGCTL MSR are saved 
into the corresponding fields. The first processors to support the virtual-machine extensions supported only the 
1-setting of this control and thus always saved data into these fields.

•

If the “save IA32_PAT” VM-exit control is 1, the contents of the IA32_PAT MSR are saved into the corresponding 
field.

•

If the “save IA32_EFER” VM-exit control is 1, the contents of the IA32_EFER MSR are saved into the corre-
sponding field.

17:15

Segment register:

0: ES

1: CS

2: SS

3: DS

4: FS

5: GS

Other values not used. Undefined for register instructions (bit 10 is set).

21:18

IndexReg (encoded as Reg1 above)
Undefined for register instructions (bit 10 is set) and for memory instructions with no index register (bit 10 is clear 

and bit 22 is set).

22

IndexReg invalid (0 = valid; 1 = invalid)
Undefined for register instructions (bit 10 is set).

26:23

BaseReg (encoded as Reg1 above)
Undefined for register instructions (bit 10 is set) and for memory instructions with no base register (bit 10 is clear 

and bit 27 is set).

27

BaseReg invalid (0 = valid; 1 = invalid)
Undefined for register instructions (bit 10 is set).

31:28

Reg2 (same encoding as Reg1 above)

Table 27-14.  Format of the VM-Exit Instruction-Information Field as Used for VMREAD and VMWRITE (Contd.)

Bit Position(s) Content