15-20 Vol. 3B

MACHINE-CHECK ARCHITECTURE

15.9 

INTERPRETING THE MCA ERROR CODES

When the processor detects a machine-check error condition, it writes a 16-bit error code to the MCA error code 
field of one of the IA32_MCi_STATUS registers and sets the VAL (valid) flag in that register. The processor may also 
write a 16-bit model-specific error code in the IA32_MCi_STATUS register depending on the implementation of the 
machine-check architecture of the processor.
The MCA error codes are architecturally defined for Intel 64 and IA-32 processors. To determine the cause of a 
machine-check exception, the machine-check exception handler must read the VAL flag for each 
IA32_MCi_STATUS register. If the flag is set, the machine check-exception handler must then read the MCA error 
code field of the register. It is the encoding of the MCA error code field [15:0] that determines the type of error 
being reported and not the register bank reporting it.
There are two types of MCA error codes: simple error codes and compound error codes. 

15.9.1 

Simple Error Codes

Table 15-8 shows the simple error codes. These unique codes indicate global error information.

15.9.2 

Compound Error Codes

Compound error codes describe errors related to the TLBs, memory, caches, bus and interconnect logic, and 
internal timer. A set of sub-fields is common to all of compound errors. These sub-fields describe the type of access, 
level in the cache hierarchy, and type of request. Table 15-9 shows the general form of the compound error codes. 

Table 15-8.  IA32_MCi_Status [15:0] Simple Error Code Encoding 

Error Code

Binary Encoding

Meaning

No Error

0000 0000 0000 0000

No error has been reported to this bank of error-reporting 

registers.

Unclassified

0000 0000 0000 0001

This error has not been classified into the MCA error classes.

Microcode ROM Parity Error

0000 0000 0000 0010

Parity error in internal microcode ROM

External Error

0000 0000 0000 0011

The BINIT# from another processor caused this processor to 

enter machine check.

1

FRC Error

0000 0000 0000 0100

FRC (functional redundancy check) master/slave error

Internal Parity Error

0000 0000 0000 0101

Internal parity error.

SMM Handler Code Access 

Violation

0000 0000 0000 0110

An attempt was made by the SMM Handler to execute 

outside the ranges specified by SMRR.

Internal Timer Error

0000 0100 0000 0000

Internal timer error.

I/O Error

0000 1110 0000 1011

generic I/O error.

Internal Unclassified

0000 01xx  xxxx  xxxx

Internal unclassified errors. 

2

NOTES:

1. BINIT# assertion will cause a machine check exception if the processor (or any processor on the same external bus) has BINIT# 

observation enabled during power-on configuration (hardware strapping) and if machine check exceptions are enabled (by setting 

CR4.MCE = 1).

2. At least one X must equal one. Internal unclassified errors have not been classified. 

Table 15-9.  IA32_MCi_Status [15:0] Compound Error Code Encoding 

Type

Form

Interpretation

Generic Cache Hierarchy

000F 0000 0000 11LL

Generic cache hierarchy error

TLB Errors

000F 0000 0001 TTLL

{TT}TLB{LL}_ERR

Memory Controller Errors

000F 0000 1MMM CCCC

{MMM}_CHANNEL{CCCC}_ERR