16-14 Vol. 3B

INTERPRETING MACHINE-CHECK ERROR CODES

16.5.2   Integrated Memory Controller Machine Check Errors

MC error codes associated with integrated memory controllers are reported in the MSRs IA32_MC9_STATUS-
IA32_MC16_STATUS. The supported error codes are follows the architectural MCACOD definition type 1MMMCCCC 
(see Chapter 15, “Machine-Check Architecture,”). 
MSR_ERROR_CONTROL.[bit 1] can enable additional information logging of the IMC. The additional error informa-
tion logged by the IMC is stored in IA32_MCi_STATUS and IA32_MCi_MISC; (i = 9-16).

Table 16-18.  Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 9-16)

7Ah - MC_HA_FAILSTS_CHANGE_DETECTED
7Bh - MC_PCIE_R2PCIE-RW_BLOCK_ACK_TIMEOUT
81h - MC_RECOVERABLE_DIE_THERMAL_TOO_HOT

56-32

Reserved

Reserved

Status register 

validity  indicators

1

 

57-63

NOTES:

1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.

Type

Bit No.  Bit Function 

Bit Description

MCA error codes

1

 

NOTES:

1. These fields are architecturally defined. Refer to Chapter 15, “Machine-Check Architecture,” for more information.

0-15

MCACOD

Memory Controller error format: 000F 0000 1MMM CCCC

Model specific 

errors

31:16

Reserved except for 

the following

001H - Address parity error
002H - HA Wrt buffer Data parity error
004H - HA Wrt byte enable parity error
008H - Corrected patrol scrub error
010H - Uncorrected patrol scrub error
020H - Corrected spare error
040H - Uncorrected spare error
080H - Corrected memory read error. (Only applicable with iMC’s “Additional 

Error logging” Mode-1 enabled.) 
100H - iMC, WDB, parity errors

36-32

Other info

When MSR_ERROR_CONTROL.[1] is set,

 logs an encoded value from the first error 

device.

37

Reserved

Reserved

56-38

See Chapter 15, “Machine-Check Architecture,”

Status register 

validity  indicators

1

 

57-63

Type

Bit No.  Bit Function 

Bit Description