22-30 Vol. 3B

ARCHITECTURE COMPATIBILITY

prefetch queue, the P6 family and Pentium processors flush the prefetch queue, eliminating the need to code a 
jump instruction after any writes that modify an instruction. 
Because the linear address of the write is checked against the linear address of the instructions that have been 
prefetched, special care must be taken for self-modifying code to work correctly when the physical addresses of the 
instruction and the written data are the same, but the linear addresses differ. In such cases, it is necessary to 
execute a serializing operation to flush the prefetch queue after the write and before executing the modified 
instruction. See Section 8.3, “Serializing Instructions,” for more information on serializing instructions.

NOTE

The check on linear addresses described above is not in practice a concern for compatibility. Appli-
cations that include self-modifying code use the same linear address for modifying and fetching the 
instruction. System software, such as a debugger, that might possibly modify an instruction using 
a different linear address than that used to fetch the instruction must execute a serializing 
operation, such as IRET, before the modified instruction is executed.

22.29.2  Disabling the L3 Cache

A unified third-level (L3) cache in processors based on Intel NetBurst microarchitecture (see Section 11.1, 
“Internal Caches, TLBs, and Buffers”) provides the third-level cache disable flag, bit 6 of the IA32_MISC_ENABLE 
MSR. The third-level cache disable flag allows the L3 cache to be disabled and enabled, independently of the L1 and 
L2 caches (see Section 11.5.4, “Disabling and Enabling the L3 Cache”). The third-level cache disable flag applies 
only to processors based on Intel NetBurst microarchitecture. Processors with L3 and based on other microarchi-
tectures do not support the third-level cache disable flag. 

22.30 PAGING

This section identifies enhancements made to the paging mechanism and implementation differences in the paging 
mechanism for various IA-32 processors.

22.30.1 Large 

Pages

The Pentium processor extended the memory management/paging facilities of the IA-32 to allow large (4 MBytes) 
pages sizes (see Section 4.3, “32-Bit Paging”). The first P6 family processor (the Pentium Pro processor) added a 2 
MByte page size to the IA-32 in conjunction with the physical address extension (PAE) feature (see Section 4.4, 
“PAE Paging”). 
The availability of large pages with 32-bit paging on any IA-32 processor can be determined via feature bit 3 (PSE) 
of register EDX after the CPUID instruction has been execution with an argument of 1. (Large pages are always 
available with PAE paging and IA-32e paging.) Intel processors that do not support the CPUID instruction support 
only 32-bit paging and do not support page size enhancements. (See “CPUID—CPU Identification” in Chapter 3, 
“Instruction Set Reference, A-L,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 
2A for more information on the CPUID instruction.)

22.30.2  PCD and PWT Flags

The PCD and PWT flags were introduced to the IA-32 in the Intel486 processor to control the caching of pages:

•

PCD (page-level cache disable) flag—Controls caching on a page-by-page basis.

•

PWT (page-level write-through) flag—Controls the write-through/writeback caching policy on a page-by-page 
basis. Since the internal cache of the Intel486 processor is a write-through cache, it is not affected by the state 
of the PWT flag.