9-34 Vol. 3A

PROCESSOR MANAGEMENT AND INITIALIZATION

procedure treats all DWORDs as unsigned. Microcode updates with a header version equal to 00000001H must sum 
all DWORDs that comprise the microcode update. A valid checksum check will yield a value of 00000000H. Any 
other value indicates the microcode update is corrupt and should not be loaded.
The checksum algorithm shown by the pseudo code in Example 9-7 treats the microcode update as an array of 
unsigned DWORDs. If the data size DWORD field at byte offset 32 equals 00000000H, the size of the encrypted 
data is 2000 bytes, resulting in 500 DWORDs. Otherwise the microcode update size in DWORDs = (Total Size / 4), 
where the total size is a multiple of 1024 bytes (1 KBytes).

Example 9-7.  Pseudo Code Example of Checksum Test

N 

← 512

If (Update.DataSize 

≠ 00000000H)

N 

← Update.TotalSize / 4

ChkSum 

← 0

For (I 

← 0; I < N; I++)

{

ChkSum 

← ChkSum + MicrocodeUpdate[I]

}

If (ChkSum = 00000000H)

Success

Else

Fail

9.11.6 

Microcode Update Loader

This section describes an update loader used to load an update into a P6 family or later processors. It also discusses 
the requirements placed on the BIOS to ensure proper loading. The update loader described contains the minimal 
instructions needed to load an update. The specific instruction sequence that is required to load an update is 
dependent upon the loader revision field contained within the update header. This revision is expected to change 
infrequently (potentially, only when new processor models are introduced).
Example 9-8 below represents the update loader with a loader revision of 00000001H. Note that the microcode 
update must be aligned on a 16-byte boundary and the size of the microcode update must be 1-KByte granular.

Example 9-8.  Assembly Code Example of Simple Microcode Update Loader

mov

ecx,79h

; MSR to write in ECX

xor

eax,eax

; clear EAX

xor

ebx,ebx

; clear EBX

mov

ax,cs

; Segment of microcode update

shl

eax,4

mov

bx,offset Update

; Offset of microcode update

add

eax,ebx

; Linear Address of Update in EAX

add

eax,48d

; Offset of the Update Data within the Update

xor

edx,edx

; Zero in EDX

WRMSR

; microcode update trigger

The loader shown in Example 9-8 assumes that update is the address of a microcode update (header and data) 
embedded within the code segment of the BIOS. It also assumes that the processor is operating in real mode. The 
data may reside anywhere in memory, aligned on a 16-byte boundary, that is accessible by the processor within its 
current operating mode.
Before the BIOS executes the microcode update trigger (WRMSR) instruction, the following must be true: