34-16 Vol. 3C

SYSTEM MANAGEMENT MODE

34.12.1  Back-to-Back SMI Interrupts When I/O Instruction Restart Is Being Used

If an SMI interrupt is signaled while the processor is servicing an SMI interrupt that occurred on an I/O instruction 
boundary, the processor will service the new SMI request before restarting the originally interrupted I/O instruc-
tion. If the I/O instruction restart field is set to FFH prior to returning from the second SMI handler, the EIP will point 
to an address different from the originally interrupted I/O instruction, which will likely lead to a program error. To 
avoid this situation, the SMI handler must be able to recognize the occurrence of back-to-back SMI interrupts when 
I/O instruction restart is being used and insure that the handler sets the I/O instruction restart field to 00H prior to 
returning from the second invocation of the SMI handler.

34.13  SMM MULTIPLE-PROCESSOR CONSIDERATIONS

The following should be noted when designing multiple-processor systems:

•

Any processor in a multiprocessor system can respond to an SMM.

•

Each processor needs its own SMRAM space. This space can be in system memory or in a separate RAM.

•

The SMRAMs for different processors can be overlapped in the same memory space. The only stipulation is that 
each processor needs its own state save area and its own dynamic data storage area. (Also, for the Pentium 
and Intel486 processors, the SMBASE address must be located on a 32-KByte boundary.) Code and static data 
can be shared among processors. Overlapping SMRAM spaces can be done more efficiently with the P6 family 
processors because they do not require that the SMBASE address be on a 32-KByte boundary. 

•

The SMI handler will need to initialize the SMBASE for each processor.

•

Processors can respond to local SMIs through their SMI# pins or to SMIs received through the APIC interface. 
The APIC interface can distribute SMIs to different processors.

•

Two or more processors can be executing in SMM at the same time.

•

When operating Pentium processors in dual processing (DP) mode, the SMIACT# pin is driven only by the MRM 
processor and should be sampled with ADS#. For additional details, see Chapter 14 of the Pentium Processor 
Family User’s Manual, Volume 1.

SMM is not re-entrant, because the SMRAM State Save Map is fixed relative to the SMBASE. If there is a need to 
support two or more processors in SMM mode at the same time then each processor should have dedicated SMRAM 
spaces. This can be done by using the SMBASE Relocation feature (see Section 34.11).

34.14  DEFAULT TREATMENT OF SMIS AND SMM WITH VMX OPERATION AND 

SMX OPERATION

Under the default treatment, the interactions of SMIs and SMM with VMX operation are few. This section details 
those interactions. It also explains how this treatment affects SMX operation.

34.14.1  Default Treatment of SMI Delivery

Ordinary SMI delivery saves processor state into SMRAM and then loads state based on architectural definitions. 
Under the default treatment, processors that support VMX operation perform SMI delivery as follows:

enter SMM;
save the following internal to the processor:

CR4.VMXE
an indication of whether the logical processor was in VMX operation (root or non-root)

IF the logical processor is in VMX operation

THEN

save current VMCS pointer internal to the processor;
leave VMX operation;
save VMX-critical state defined below;