34-26 Vol. 3C

SYSTEM MANAGEMENT MODE

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Bytes 7:4 contain the SMM-transfer monitor features field. Bits 31:1 of this field are reserved and must be 
zero. Bit 0 of the field is the IA-32e mode SMM feature bit. It indicates whether the logical processor will be 
in IA-32e mode after the STM is activated (see Section 34.15.6).

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Bytes 31:8 contain fields that determine how processor state is loaded when the STM is activated (see Section 
34.15.6.6). SMM code should establish these fields so that activating of the STM invokes the STM’s initialization 
code. 

34.15.6  Activating the Dual-Monitor Treatment

The dual-monitor treatment may be enabled by SMM code as described in Section 34.15.5. The dual-monitor treat-
ment is activated only if it is enabled and only by the executive monitor. The executive monitor activates the dual-
monitor treatment by executing VMCALL in VMX root operation.
When VMCALL activates the dual-monitor treatment, it causes an SMM VM exit. Differences between this SMM 
VM exit and other SMM VM exits are discussed in Sections 34.15.6.1 through 34.15.6.7. See also “VMCALL—Call to 
VM Monitor” in Chapter 30.

34.15.6.1   Initial Checks

An execution of VMCALL attempts to activate the dual-monitor treatment if (1) the processor supports the dual-
monitor treatment;

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 (2) the logical processor is in VMX root operation; (3) the logical processor is outside SMM and 

the valid bit is set in the IA32_SMM_MONITOR_CTL MSR; (4) the logical processor is not in virtual-8086 mode and 
not in compatibility mode; (5) CPL = 0; and (6) the dual-monitor treatment is not active.
The VMCS that manages SMM VM exit caused by this VMCALL is the current VMCS established by the executive 
monitor. The VMCALL performs the following checks on the current VMCS in the order indicated:
1. There must be a current VMCS pointer.
2. The launch state of the current VMCS must be clear.
3. Reserved bits in the VM-exit controls in the current VMCS must be set properly. Software may consult the VMX 

capability MSR IA32_VMX_EXIT_CTLS to determine the proper settings (see Appendix A.4).

If any of these checks fail, subsequent checks are skipped and VMCALL fails. If all these checks succeed, the logical 
processor uses the IA32_SMM_MONITOR_CTL MSR to determine the base address of MSEG. The following checks 
are performed in the order indicated:
1. The logical processor reads the 32 bits at the base of MSEG and compares them to the processor’s MSEG 

revision identifier.

2. The logical processor reads the SMM-transfer monitor features field:

— Bit 0 of the field is the IA-32e mode SMM feature bit, and it indicates whether the logical processor will be 

in IA-32e mode after the SMM-transfer monitor (STM) is activated.

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If the VMCALL is executed on a processor that does not support Intel 64 architecture, the IA-32e mode 

SMM feature bit must be 0.

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If the VMCALL is executed in 64-bit mode, the IA-32e mode SMM feature bit must be 1.

— Bits 31:1 of this field are currently reserved and must be zero.

If any of these checks fail, subsequent checks are skipped and the VMCALL fails.

34.15.6.2   MSEG Checking

SMM VM exits that activate the dual-monitor treatment check the following before updating the current-VMCS 
pointer and the executive-VMCS pointer field (see Section 34.15.2.2):

1. Software should consult the VMX capability MSR IA32_VMX_BASIC (see Appendix A.1) to determine whether the dual-monitor 

treatment is supported.