11-6 Vol. 3A

MEMORY CACHE CONTROL

When operating in an MP system, IA-32 processors (beginning with the Intel486 processor) and Intel 64 processors 
have the ability to snoop other processor’s accesses to system memory and to their internal caches. They use this 
snooping ability to keep their internal caches consistent both with system memory and with the caches in other 
processors on the bus. For example, in the Pentium and P6 family processors, if through snooping one processor 
detects that another processor intends to write to a memory location that it currently has cached in shared state, 
the snooping processor will invalidate its cache line forcing it to perform a cache line fill the next time it accesses 
the same memory location. 
Beginning with the P6 family processors, if a processor detects (through snooping) that another processor is trying 
to access a memory location that it has modified in its cache, but has not yet written back to system memory, the 
snooping processor will signal the other processor (by means of the HITM# signal) that the cache line is held in 
modified state and will preform an implicit write-back of the modified data. The implicit write-back is transferred 
directly to the initial requesting processor and snooped by the memory controller to assure that system memory 
has been updated. Here, the processor with the valid data may pass the data to the other processors without actu-
ally writing it to system memory; however, it is the responsibility of the memory controller to snoop this operation 
and update memory.

11.3 

METHODS OF CACHING AVAILABLE

The processor allows any area of system memory to be cached in the L1, L2, and L3 caches. In individual pages or 
regions of system memory, it allows the type of caching (also called memory type) to be specified (see Section 
11.5). Memory types currently defined for the Intel 64 and IA-32 architectures are (see Table 11-2):

•

Strong Uncacheable (UC) —System memory locations are not cached. All reads and writes appear on the 
system bus and are executed in program order without reordering. No speculative memory accesses, page-
table walks, or prefetches of speculated branch targets are made. This type of cache-control is useful for 
memory-mapped I/O devices. When used with normal RAM, it greatly reduces processor performance.

NOTE

The behavior of FP and SSE/SSE2 operations on operands in UC memory is implementation 
dependent. In some implementations, accesses to UC memory may occur more than once. To 
ensure predictable behavior, use loads and stores of general purpose registers to access UC 
memory that may have read or write side effects.

•

Uncacheable (UC-) — Has same characteristics as the strong uncacheable (UC) memory type, except that 
this memory type can be overridden by programming the MTRRs for the WC memory type. This memory type 
is available in processor families starting from the Pentium III processors and can only be selected through the 
PAT.

Table 11-2.  Memory Types and Their Properties

Memory Type and 

Mnemonic

Cacheable

Writeback 

Cacheable

Allows

Speculative 

Reads

Memory Ordering Model

Strong Uncacheable 

(UC)

No

No

No

Strong Ordering

Uncacheable (UC-)

No

No

No

Strong Ordering. Can only be selected through the PAT. Can be 

overridden by WC in MTRRs.

Write Combining (WC) No

No

Yes

Weak Ordering. Available by programming MTRRs or by selecting it 

through the PAT.

Write Through (WT)

Yes

No

Yes

Speculative Processor Ordering.

Write Back (WB)

Yes

Yes

Yes

Speculative Processor Ordering.

Write Protected (WP) Yes for 

reads; no for 

writes

No

Yes

Speculative Processor Ordering. Available by programming MTRRs.