Vol. 3B 22-5

ARCHITECTURE COMPATIBILITY

The following instructions were added in the Intel386 processor:

•

LSS, LFS, and LGS (load SS, FS, and GS registers).

•

Long-displacement conditional jumps.

•

Single-bit instructions.

•

Bit scan instructions.

•

Double-shift instructions.

•

Byte set on condition instruction.

•

Move with sign/zero extension.

•

Generalized multiply instruction.

•

MOV to and from control registers.

•

MOV to and from test registers (now obsolete).

•

MOV to and from debug registers.

•

RSM (resume from SMM). This instruction was introduced in the Intel386 SL and Intel486 SL processors.

The following instructions were added in the Intel 387 math coprocessor:

•

FPREM1.

•

FUCOM, FUCOMP, and FUCOMPP.

22.14 OBSOLETE 

INSTRUCTIONS

The MOV to and from test registers instructions were removed from the Pentium processor and future IA-32 
processors. Execution of these instructions generates an invalid-opcode exception (#UD).

22.15 UNDEFINED 

OPCODES

All new instructions defined for IA-32 processors use binary encodings that were reserved on earlier-generation 
processors. Attempting to execute a reserved opcode always results in an invalid-opcode (#UD) exception being 
generated. Consequently, programs that execute correctly on earlier-generation processors cannot erroneously 
execute these instructions and thereby produce unexpected results when executed on later IA-32 processors.

22.16  NEW FLAGS IN THE EFLAGS REGISTER

The section titled “EFLAGS Register” in Chapter 3, “Basic Execution Environment,” of the Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volume 1, shows the configuration of flags in the EFLAGS register for 
the P6 family processors. No new flags have been added to this register in the P6 family processors. The flags 
added to this register in the Pentium and Intel486 processors are described in the following sections.
The following flags were added to the EFLAGS register in the Pentium processor:

•

VIF (virtual interrupt flag), bit 19.

•

VIP (virtual interrupt pending), bit 20. 

NOTES:

1. The RDPMC instruction was introduced in the P6 family of processors and added to later model Pentium processors. This instruc-

tion is model specific in nature and not architectural.

2. The CPUID instruction is available in all Pentium and P6 family processors and in later models of the Intel486 processors. The ability 

to set and clear the ID flag (bit 21) in the EFLAGS register indicates the availability of the CPUID instruction.

Table 22-1.  New Instruction in the Pentium Processor and Later IA-32 Processors (Contd.)

Instruction

CPUID Identification Bits

Introduced In