Vol. 3A 8-11

MULTIPLE-PROCESSOR MANAGEMENT

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Because the memory-ordering model prevents a store from being reordered with an earlier load (see Section 
8.2.3.3), processor 1’s load occurs before its store. Thus, processor 0’s store causally precedes processor 1’s 
store.

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Because processor 0’s store causally precedes processor 1’s store, the memory-ordering model ensures that 
processor 0’s store appears to occur before processor 1’s store from the point of view of all processors.

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Because r2 = 1, processor 1’s store occurs before processor 2’s load.

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Because the Intel-64 memory-ordering model prevents loads from being reordered (see Section 8.2.3.2), 
processor 2’s load occur in order.

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The above items imply that processor 0’s store to x occurs before processor 2’s load from x. This implies that 
r3 = 1.

8.2.3.7  

Stores Are Seen in a Consistent Order by Other Processors

As noted in Section 8.2.3.5, the memory-ordering model allows stores by two processors to be seen in different 
orders by those two processors. However, any two stores must appear to execute in the same order to all proces-
sors other than those performing the stores. This is illustrated by the following example:

By the principles discussed in Section 8.2.3.2, 

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processor 2’s first and second load cannot be reordered,

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processor 3’s first and second load cannot be reordered. 

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If r1 = 1 and r2 = 0, processor 0’s store appears to precede processor 1’s store with respect to processor 2. 

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Similarly, r3 = 1 and r4 = 0 imply that processor 1’s store appears to precede processor 0’s store with respect 
to processor 1. 

Because the memory-ordering model ensures that any two stores appear to execute in the same order to all 
processors (other than those performing the stores), this set of return values is not allowed

8.2.3.8  

Locked Instructions Have a Total Order

The memory-ordering model ensures that all processors agree on a single execution order of all locked instruc-
tions, including those that are larger than 8 bytes or are not naturally aligned. This is illustrated by the following 
example:

Processor 2 and processor 3 must agree on the order of the two executions of XCHG. Without loss of generality, 
suppose that processor 0’s XCHG occurs first.

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If r5 = 1, processor 1’s XCHG into y occurs before processor 3’s load from y.

Example 8-7.  Stores Are Seen in a Consistent Order by Other Processors

Processor 0

Processor 1

Processor 2

Processor 3

mov [ _x], 1 

mov [ _y], 1

mov r1, [ _x] 

mov r3, [_y] 

mov r2, [ _y] 

mov r4, [_x] 

Initially x = y =0
r1 = 1, r2 = 0, r3 = 1, r4 = 0 is not allowed

Example 8-8.  Locked Instructions Have a Total Order

Processor 0

Processor 1

Processor 2

Processor 3

xchg [ _x], r1

xchg [ _y], r2

mov r3, [ _x]

mov r5, [_y]

mov r4, [ _y]

mov r6, [_x]

Initially r1 = r2 = 1, x = y = 0
r3 = 1, r4 = 0, r5 = 1, r6 = 0 is not allowed