29-2 Vol. 3C

APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS

•

Virtual processor-priority register (VPPR): the 32-bit field located at offset 0A0H on the virtual-APIC 
page.

•

Virtual end-of-interrupt register (VEOI): the 32-bit field located at offset 0B0H on the virtual-APIC page.

•

Virtual interrupt-service register (VISR): the 256-bit value comprising eight non-contiguous 32-bit fields 
at offsets 100H, 110H, 120H, 130H, 140H, 150H, 160H, and 170H on the virtual-APIC page. Bit x of the VISR 
is at bit position (x & 1FH) at offset (100H | ((x & E0H) » 1)). The processor uses only the low 4 bytes of each 
of the 16-byte fields at offsets 100H, 110H, 120H, 130H, 140H, 150H, 160H, and 170H.

•

Virtual interrupt-request register (VIRR): the 256-bit value comprising eight non-contiguous 32-bit fields 
at offsets 200H, 210H, 220H, 230H, 240H, 250H, 260H, and 270H on the virtual-APIC page. Bit x of the VIRR 
is at bit position (x & 1FH) at offset (200H | ((x & E0H) » 1)). The processor uses only the low 4 bytes of each 
of the 16-Byte fields at offsets 200H, 210H, 220H, 230H, 240H, 250H, 260H, and 270H.

•

Virtual interrupt-command register (VICR_LO): the 32-bit field located at offset 300H on the virtual-APIC 
page

•

Virtual interrupt-command register (VICR_HI): the 32-bit field located at offset 310H on the virtual-APIC 
page.

29.1.2 TPR 

Virtualization

The processor performs TPR virtualization in response to the following operations: (1) virtualization of the MOV 
to CR8 instruction; (2) virtualization of a write to offset 080H on the APIC-access page; and (3) virtualization of the 
WRMSR instruction with ECX = 808H. See Section 29.3, Section 29.4.3, and Section 29.5 for details of when TPR 
virtualization is performed.
The following pseudocode details the behavior of TPR virtualization:

IF “virtual-interrupt delivery” is 0

THEN

IF VTPR[7:4] < TPR threshold (see Section 24.6.8)

THEN cause VM exit due to TPR below threshold;

FI;

ELSE

perform PPR virtualization (see Section 29.1.3);
evaluate pending virtual interrupts (see Section 29.2.1);

FI;

Any VM exit caused by TPR virtualization is trap-like: the instruction causing TPR virtualization completes before 
the VM exit occurs (for example, the value of CS:RIP saved in the guest-state area of the VMCS references the next 
instruction).

29.1.3 PPR 

Virtualization

The processor performs PPR virtualization in response to the following operations: (1) VM entry; (2) TPR virtu-
alization; and (3) EOI virtualization. See Section 26.3.2.5, Section 29.1.2, and Section 29.1.4 for details of when 
PPR virtualization is performed.
PPR virtualization uses the guest interrupt status (specifically, SVI; see Section 24.4.2) and VTPR. The following 
pseudocode details the behavior of PPR virtualization:

IF VTPR[7:4] ≥ SVI[7:4]

THEN VPPR ← VTPR & FFH;

ELSE VPPR ← SVI & F0H;

FI;

PPR virtualization always clears bytes 3:1 of VPPR.
PPR virtualization is caused only by TPR virtualization, EOI virtualization, and VM entry. Delivery of a virtual inter-
rupt also modifies VPPR, but in a different way (see Section 29.2.2). No other operations modify VPPR, even if they 
modify SVI, VISR, or VTPR.