Vol. 3A 4-41

PAGING

— Any PDE-cache entry associated with linear addresses with 0 in bits 47:21 contains address X for similar 

reasons.

— Any TLB entry for page number 0 (associated with linear addresses with 0 in bits 47:12) translates to page 

frame X » 12 for similar reasons.

The same PML4E contributes its address X to all these cache entries because the self-referencing nature of the 
entry causes it to be used as a PML4E, a PDPTE, a PDE, and a PTE.

4.10.4 

Invalidation of TLBs and Paging-Structure Caches

As noted in Section 4.10.2 and Section 4.10.3, the processor may create entries in the TLBs and the paging-struc-
ture caches when linear addresses are translated, and it may retain these entries even after the paging structures 
used to create them have been modified. To ensure that linear-address translation uses the modified paging struc-
tures, software should take action to invalidate any cached entries that may contain information that has since 
been modified.

4.10.4.1   Operations that Invalidate TLBs and Paging-Structure Caches

The following instructions invalidate entries in the TLBs and the paging-structure caches:

•

INVLPG. This instruction takes a single operand, which is a linear address. The instruction invalidates any TLB 
entries that are for a page number corresponding to the linear address and that are associated with the current 
PCID. It also invalidates any global TLB entries with that page number, regardless of PCID (see Section 
4.10.2.4).

1

 INVLPG also invalidates all entries in all paging-structure caches associated with the current PCID, 

regardless of the linear addresses to which they correspond.

•

INVPCID. The operation of this instruction is based on instruction operands, called the INVPCID type and the 
INVPCID descriptor. Four INVPCID types are currently defined:
— Individual-address. If the INVPCID type is 0, the logical processor invalidates mappings—except global 

translations—associated with the PCID specified in the INVPCID descriptor and that would be used to 
translate the linear address specified in the INVPCID descriptor.

2

 (The instruction may also invalidate global 

translations, as well as mappings associated with other PCIDs and for other linear addresses.)

— Single-context. If the INVPCID type is 1, the logical processor invalidates all mappings—except global 

translations—associated with the PCID specified in the INVPCID descriptor. (The instruction may also 
invalidate global translations, as well as mappings associated with other PCIDs.)

— All-context, including globals. If the INVPCID type is 2, the logical processor invalidates 

mappings—including global translations—associated with all PCIDs.

— All-context. If the INVPCID type is 3, the logical processor invalidates mappings—except global transla-

tions—associated with all PCIDs. (The instruction may also invalidate global translations.)

See Chapter 3 of the Intel 64 and IA-32 Architecture Software Developer’s Manual, Volume 2A for details of the 
INVPCID instruction.

•

MOV to CR0. The instruction invalidates all TLB entries (including global entries) and all entries in all paging-
structure caches (for all PCIDs) if it changes the value of CR0.PG from 1 to 0.

•

MOV to CR3. The behavior of the instruction depends on the value of CR4.PCIDE:
— If CR4.PCIDE = 0, the instruction invalidates all TLB entries associated with PCID 000H except those for 

global pages. It also invalidates all entries in all paging-structure caches associated with PCID 000H.

— If CR4.PCIDE = 1 and bit 63 of the instruction’s source operand is 0, the instruction invalidates all TLB 

entries associated with the PCID specified in bits 11:0 of the instruction’s source operand except those for 
global pages. It also invalidates all entries in all paging-structure caches associated with that PCID. It is not 
required to invalidate entries in the TLBs and paging-structure caches that are associated with other PCIDs.

1. If the paging structures map the linear address using a page larger than 4 KBytes and there are multiple TLB entries for that page 

(see Section 4.10.2.3), the instruction invalidates all of them.

2. If the paging structures map the linear address using a page larger than 4 KBytes and there are multiple TLB entries for that page 

(see Section 4.10.2.3), the instruction invalidates all of them.