Vol. 3B 18-115

PERFORMANCE MONITORING

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FSB_L_hitm (bit 40): Count HITM snoop results from any source for transaction originated from this physical 
package

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FSB_L_defer (bit 41): Count DEFER responses to this processor’s transactions

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FSB_L_retry (bit 42): Count RETRY responses to this processor’s transactions

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FSB_L_snoop_stall (bit 43): Count snoop stalls to this processor’s transactions

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FSB_DBSY (bit 44): Count DBSY assertions by this processor (without a concurrent DRDY)

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FSB_DRDY (bit 45): Count DRDY assertions by this processor

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FSB_BNR (bit 46): Count BNR assertions by this processor

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FSB_IOQ_empty (bit 47): Counts each bus clocks when the IOQ is empty

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FSB_IOQ_full (bit 48): Counts each bus clocks when the IOQ is full

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FSB_IOQ_active (bit 49): Counts each bus clocks when there is at least one entry in the IOQ

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FSB_WW_data (bit 50): Counts back-to-back write transaction’s data phase.

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FSB_WW_issue (bit 51): Counts back-to-back write transaction request pairs issued by this processor.

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FSB_WR_issue (bit 52): Counts back-to-back write-read transaction request pairs issued by this processor.

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FSB_RW_issue (bit 53): Counts back-to-back read-write transaction request pairs issued by this processor.

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FSB_other_DBSY (bit 54): Count DBSY assertions by another agent (without a concurrent DRDY)

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FSB_other_DRDY (bit 55): Count DRDY assertions by another agent

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FSB_other_snoop_stall (bit 56): Count snoop stalls on the FSB due to another agent

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FSB_other_BNR (bit 57): Count BNR assertions from another agent

18.21.5  Common Event Control Interface

The MSR_EMON_L3_GL_CTL MSR provides simplified access to query overflow status of the GBSQ, GSNPQ, FSB 
event counters. It also provides control bit fields to freeze, unfreeze, or reset those counters. The following bit 
fields are supported:

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GL_freeze_cmd (bit 0): Freeze the event counters specified by the GL_event_select field.

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GL_unfreeze_cmd (bit 1): Unfreeze the event counters specified by the GL_event_select field.

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GL_reset_cmd (bit 2): Clear the event count field of the event counters specified by the GL_event_select field. 
The event select field is not affected.

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GL_event_select (bit 23:16): Selects one or more event counters to subject to specified command operations 
indicated by bits 2:0. Bit 16 corresponds to MSR_EMON_L3_CTR_CTL0, bit 23 corresponds to 
MSR_EMON_L3_CTR_CTL7.

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GL_event_status (bit 55:48): Indicates the overflow status of each event counters. Bit 48 corresponds to 
MSR_EMON_L3_CTR_CTL0, bit 55 corresponds to MSR_EMON_L3_CTR_CTL7.

In the event control field (bits 63:32) of each MSR, if the saturate control (bit 59, see Figure 18-57 for example) is 
set, the event logic forces the value FFFF_FFFFH into the event count field instead of incrementing it. 

18.22  PERFORMANCE MONITORING (P6 FAMILY PROCESSOR)

The P6 family processors provide two 40-bit performance counters, allowing two types of events to be monitored 
simultaneously. These can either count events or measure duration. When counting events, a counter increments 
each time a specified event takes place or a specified number of events takes place. When measuring duration, it 
counts the number of processor clocks that occur while a specified condition is true. The counters can count events 
or measure durations that occur at any privilege level. 
Table 19-37, Chapter 19, lists the events that can be counted with the P6 family performance monitoring counters.