18-98 Vol. 3B

PERFORMANCE MONITORING

18.15.7  Processor Event-Based Sampling (PEBS)

The debug store (DS) mechanism in processors based on Intel NetBurst microarchitecture allow two types of infor-
mation to be collected for use in debugging and tuning programs: PEBS records and BTS records. See Section 
17.4.5, “Branch Trace Store (BTS),” for a description of the BTS mechanism.
PEBS permits the saving of precise architectural information associated with one or more performance events in 
the precise event records buffer, which is part of the DS save area (see Section 17.4.9, “BTS and DS Save Area”). 
To use this mechanism, a counter is configured to overflow after it has counted a preset number of events. After 
the counter overflows, the processor copies the current state of the general-purpose and EFLAGS registers and 
instruction pointer into a record in the precise event records buffer. The processor then resets the count in the 
performance counter and restarts the counter. When the precise event records buffer is nearly full, an interrupt is 
generated, allowing the precise event records to be saved. A circular buffer is not supported for precise event 
records.
PEBS is supported only for a subset of the at-retirement events: Execution_event, Front_end_event, and 
Replay_event. Also, PEBS can only be carried out using the one performance counter, the MSR_IQ_COUNTER4 
MSR.
In processors based on Intel Core microarchitecture, a similar PEBS mechanism is also supported using IA32_PMC0 
and IA32_PERFEVTSEL0 MSRs (See Section 18.4.4).

18.15.7.1   Detection of the Availability of the PEBS Facilities

The DS feature flag (bit 21) returned by the CPUID instruction indicates (when set) the availability of the DS mech-
anism in the processor, which supports the PEBS (and BTS) facilities. When this bit is set, the following PEBS facil-
ities are available:

•

The PEBS_UNAVAILABLE flag in the IA32_MISC_ENABLE MSR indicates (when clear) the availability of the 
PEBS facilities, including the MSR_PEBS_ENABLE MSR. 

•

The enable PEBS flag (bit 24) in the MSR_PEBS_ENABLE MSR allows PEBS to be enabled (set) or disabled 
(clear).

•

The IA32_DS_AREA MSR can be programmed to point to the DS save area. 

18.15.7.2   Setting Up the DS Save Area

Section 17.4.9.2, “Setting Up the DS Save Area,” describes how to set up and enable the DS save area. This proce-
dure is common for PEBS and BTS.

18.15.7.3   Setting Up the PEBS Buffer

Only the MSR_IQ_COUNTER4 performance counter can be used for PEBS. Use the following procedure to set up the 
processor and this counter for PEBS: 
1. Set up the precise event buffering facilities. Place values in the precise event buffer base, precise event index, 

precise event absolute maximum, and precise event interrupt threshold, and precise event counter reset fields 
of the DS buffer management area (see Figure 17-5) to set up the precise event records buffer in memory.

2. Enable PEBS. Set the Enable PEBS flag (bit 24) in MSR_PEBS_ENABLE MSR.
3. Set up the MSR_IQ_COUNTER4 performance counter and its associated CCCR and one or more ESCRs for PEBS 

as described in Tables 19-29 through 19-33.

18.15.7.4   Writing a PEBS Interrupt Service Routine 

The PEBS facilities share the same interrupt vector and interrupt service routine (called the DS ISR) with the non-
precise event-based sampling and BTS facilities. To handle PEBS interrupts, PEBS handler code must be included in 
the DS ISR. See Section 17.4.9.5, “Writing the DS Interrupt Service Routine,” for guidelines for writing the DS ISR.