20-12 Vol. 3B
8086 EMULATION
Register”). This field also controls the enabling of the VIF and VIP flags in the EFLAGS register when the VME
flag is set. The VIF and VIP flags are provided to assist in the handling of class 2 maskable hardware interrupts.
•
VME flag (bit 0 in control register CR4) — Enables the virtual mode extension for the processor when set
(see Section 2.5, “Control Registers”).
•
Software interrupt redirection bit map (32 bytes in the TSS, see Figure 20-5) — Contains 256 flags
that indicates how class 3 software interrupts should be handled when they occur in virtual-8086 mode. A
software interrupt can be directed either to the interrupt and exception handlers in the currently running 8086
program or to the protected-mode interrupt and exception handlers.
•
The virtual interrupt flag (VIF) and virtual interrupt pending flag (VIP) in the EFLAGS register —
Provides virtual interrupt support for the handling of class 2 maskable hardware interrupts (see Section
20.3.2, “Class 2—Maskable Hardware Interrupt Handling in Virtual-8086 Mode Using the Virtual Interrupt
Mechanism”).
NOTE
The VME flag, software interrupt redirection bit map, and VIF and VIP flags are only available in IA-
32 processors that support the virtual mode extensions. These extensions were introduced in the
IA-32 architecture with the Pentium processor.
The following sections describe the actions that processor takes and the possible actions of interrupt and exception
handlers for the two classes of interrupts described in the previous paragraphs. These sections describe three
possible types of interrupt and exception handlers:
•
Protected-mode interrupt and exceptions handlers — These are the standard handlers that the processor
calls through the protected-mode IDT.
•
Virtual-8086 monitor interrupt and exception handlers — These handlers are resident in the virtual-8086
monitor, and they are commonly accessed through a general-protection exception (#GP, interrupt 13) that is
directed to the protected-mode general-protection exception handler.
•
8086 program interrupt and exception handlers — These handlers are part of the 8086 program that is
running in virtual-8086 mode.
The following sections describe how these handlers are used, depending on the selected class and method of inter-
rupt and exception handling.
20.3.1
Class 1—Hardware Interrupt and Exception Handling in Virtual-8086 Mode
In virtual-8086 mode, the Pentium, P6 family, Pentium 4, and Intel Xeon processors handle hardware interrupts
and exceptions in the same manner as they are handled by the Intel486 and Intel386 processors. They invoke the
protected-mode interrupt or exception handler that the interrupt or exception vector points to in the IDT. Here, the
IDT entry must contain either a 32-bit trap or interrupt gate or a task gate. The following sections describe various
ways that a virtual-8086 mode interrupt or exception can be handled after the protected-mode handler has been
invoked.
See Section 20.3.2, “Class 2—Maskable Hardware Interrupt Handling in Virtual-8086 Mode Using the Virtual Inter-
rupt Mechanism”, for a description of the virtual interrupt mechanism that is available for handling maskable hard-
ware interrupts while in virtual-8086 mode. When this mechanism is either not available or not enabled, maskable
hardware interrupts are handled in the same manner as exceptions, as described in the following sections.
20.3.1.1 Handling an Interrupt or Exception Through a Protected-Mode Trap or Interrupt Gate
When an interrupt or exception vector points to a 32-bit trap or interrupt gate in the IDT, the gate must in turn
point to a nonconforming, privilege-level 0, code segment. When accessing this code segment, processor performs
the following steps.
1. Switches to 32-bit protected mode and privilege level 0.
2. Saves the state of the processor on the privilege-level 0 stack. The states of the EIP, CS, EFLAGS, ESP, SS, ES,
DS, FS, and GS registers are saved (see Figure 20-4).