Vol. 3C 26-5

VM ENTRIES

•

Bits 11:0 of the address must be 0.

•

The address must not set any bits beyond the processor’s physical-address width.

If the “enable VM functions” processor-based VM-execution control is 0, no checks are performed on the VM-
function controls.

•

If the “VMCS shadowing” VM-execution control is 1, the VMREAD-bitmap and VMWRITE-bitmap addresses 
must each satisfy the following checks:

1

— Bits 11:0 of the address must be 0.
— The address must not set any bits beyond the processor’s physical-address width.

•

If the “EPT-violation #VE” VM-execution control is 1, the virtualization-exception information address must 
satisfy the following checks:

2

— Bits 11:0 of the address must be 0.
— The address must not set any bits beyond the processor’s physical-address width.

26.2.1.2   VM-Exit Control Fields

VM entries perform the following checks on the VM-exit control fields.

•

Reserved bits in the VM-exit controls must be set properly. Software may consult the VMX capability MSRs to 
determine the proper settings (see Appendix A.4).

•

If the “activate VMX-preemption timer” VM-execution control is 0, the “save VMX-preemption timer value” VM-
exit control must also be 0.

•

The following checks are performed for the VM-exit MSR-store address if the VM-exit MSR-store count field is 
non-zero:
— The lower 4 bits of the VM-exit MSR-store address must be 0. The address should not set any bits beyond 

the processor’s physical-address width.

3

— The address of the last byte in the VM-exit MSR-store area should not set any bits beyond the processor’s 

physical-address width. The address of this last byte is VM-exit MSR-store address + (MSR count * 16) – 
1. (The arithmetic used for the computation uses more bits than the processor’s physical-address width.)

If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits in the range 63:32; see Appendix
A.1.

•

The following checks are performed for the VM-exit MSR-load address if the VM-exit MSR-load count field is 
non-zero:
— The lower 4 bits of the VM-exit MSR-load address must be 0. The address should not set any bits beyond 

the processor’s physical-address width.

— The address of the last byte in the VM-exit MSR-load area should not set any bits beyond the processor’s 

physical-address width. The address of this last byte is VM-exit MSR-load address + (MSR count * 16) – 1. 
(The arithmetic used for the computation uses more bits than the processor’s physical-address width.)

If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits in the range 63:32; see Appendix
A.1.

26.2.1.3   VM-Entry Control Fields

VM entries perform the following checks on the VM-entry control fields.

1. “VMCS shadowing” is a secondary processor-based VM-execution control. If bit 31 of the primary processor-based VM-execution 

controls is 0, VM entry functions as if the “VMCS shadowing” VM-execution control were 0. See Section 24.6.2.

2. “EPT-violation #VE” is a secondary processor-based VM-execution control. If bit 31 of the primary processor-based VM-execution 

controls is 0, VM entry functions as if the “EPT-violation #VE” VM-execution control were 0. See Section 24.6.2.

3. Software can determine a processor’s physical-address width by executing CPUID with 80000008H in EAX. The physical-address 

width is returned in bits 7:0 of EAX.