14-14 Vol. 3B

POWER AND THERMAL MANAGEMENT

14.5.2 

Package level Enabling HDC

The layout of the IA32_PKG_HDC_CTL MSR is shown in Figure 14-12. IA32_PKG_HDC_CTL is a writable MSR from 
any logical processor in a package. The bit fields are described below: 

•

HDC_PKG_Enable (bit 0, R/W) — Software sets this bit to enable HDC operation by allowing the processor 
to force to idle all “HDC-allowed” (see Figure 14.5.3) logical processors in the package. Clearing this bit 
disables HDC operation in the package by waking up all the processor cores that were forced into idle by a 
previous ‘0’-to-’1’ transition in IA32_PKG_HDC_CTL.HDC_PKG_Enable. This bit is writable only if 
CPUID.06H:EAX[bit 13] = 1. Default = zero (0). 

•

Bits 63:1 are reserved and must be zero.

After processor support is determined via CPUID, system software can enable HDC operation by setting 
IA32_PKG_HDC_CTL.HDC_PKG_Enable to 1. At reset, IA32_PKG_HDC_CTL.HDC_PKG_Enable is cleared to 0. A 
'0'-to-'1' transition in HDC_PKG_Enable allows the processor to force to idle all HDC-allowed (indicated by the non-
zero state of IA32_PM_CTL1[bit 0]) logical processors in the package. A ‘1’-to-’0’ transition wakes up those HDC 
force-idled logical processors. 
Software can enable or disable HDC using this package level control multiple times from any logical processor in the 
package. Note the latency of writing a value to the package-visible IA32_PKG_HDC_CTL.HDC_PKG_Enable is 
longer than the latency of a WRMSR operation to a Logical Processor MSR (as opposed to package level MSR) such 
as: IA32_PM_CTL1 (described in Section 14.5.3). Propagation of the change in 
IA32_PKG_HDC_CTL.HDC_PKG_Enable and reaching all HDC idled logical processor to be woken up may take on 
the order of core C6 exit latency.

14.5.3 

Logical-Processor Level HDC Control

The layout of the IA32_PM_CTL1 MSR is shown in Figure 14-13. Each logical processor in a package has its own 
IA32_PM_CTL1 MSR. The bit fields are described below: 

DB0H

Y

IA32_PKG_HDC_CTL

Package Enable/Disable HDC.

DB1H

Y

IA32_PM_CTL1

Per-logical-processor select control to allow/block HDC forced idling. 

DB2H

Y

IA32_THREAD_STALL

Accumulate stalled cycles on this logical processor due to HDC forced idling.

653H

N

MSR_CORE_HDC_RESIDENCY

Core level stalled cycle counter due to HDC forced idling on one or more 

logical processor.

655H

N

MSR_PKG_HDC_SHALLOW_RE

SIDENCY

Accumulate the cycles the package was in C2

1

 state and at least one logical 

processor was in forced idle

656H

N

MSR_PKG_HDC_DEEP_RESIDE

NCY

Accumulate the cycles the package was in the software specified Cx

1

 state 

and at least one logical processor was in forced idle. Cx is specified in 

MSR_PKG_HDC_CONFIG_CTL.

652H

N

MSR_PKG_HDC_CONFIG_CTL

HDC configuration controls

NOTES:

1. The package “C-states” referred to in this section are processor-specific C-states.

Figure 14-12.  IA32_PKG_HDC_CTL MSR

Table 14-2.  Architectural and non-Architecture MSRs Related to HDC

63

0

Reserved

1

HDC_PKG_Enable

Reserved