Vol. 3A 7-3

TASK MANAGEMENT

to handle an interrupt or exception, the IDT entry for the interrupt or exception must contain a task gate that holds 
the selector for the interrupt- or exception-handler TSS. 
When a task is dispatched for execution, a task switch occurs between the currently running task and the 
dispatched task. During a task switch, the execution environment of the currently executing task (called the task’s 
state or context) is saved in its TSS and execution of the task is suspended. The context for the dispatched task is 
then loaded into the processor and execution of that task begins with the instruction pointed to by the newly loaded 
EIP register. If the task has not been run since the system was last initialized, the EIP will point to the first instruc-
tion of the task’s code; otherwise, it will point to the next instruction after the last instruction that the task 
executed when it was last active.
If the currently executing task (the calling task) called the task being dispatched (the called task), the TSS 
segment selector for the calling task is stored in the TSS of the called task to provide a link back to the calling task.
For all IA-32 processors, tasks are not recursive. A task cannot call or jump to itself.
Interrupts and exceptions can be handled with a task switch to a handler task. Here, the processor performs a task 
switch to handle the interrupt or exception and automatically switches back to the interrupted task upon returning 
from the interrupt-handler task or exception-handler task. This mechanism can also handle interrupts that occur 
during interrupt tasks.
As part of a task switch, the processor can also switch to another LDT, allowing each task to have a different logical-
to-physical address mapping for LDT-based segments. The page-directory base register (CR3) also is reloaded on a 
task switch, allowing each task to have its own set of page tables. These protection facilities help isolate tasks and 
prevent them from interfering with one another. 
If protection mechanisms are not used, the processor provides no protection between tasks. This is true even with 
operating systems that use multiple privilege levels for protection. A task running at privilege level 3 that uses the 
same LDT and page tables as other privilege-level-3 tasks can access code and corrupt data and the stack of other 
tasks.
Use of task management facilities for handling multitasking applications is optional. Multitasking can be handled in 
software, with each software defined task executed in the context of a single IA-32 architecture task.

7.2 

TASK MANAGEMENT DATA STRUCTURES

The processor defines five data structures for handling task-related activities:

•

Task-state segment (TSS).

•

Task-gate descriptor.

•

TSS descriptor.

•

Task register.

•

NT flag in the EFLAGS register.

When operating in protected mode, a TSS and TSS descriptor must be created for at least one task, and the 
segment selector for the TSS must be loaded into the task register (using the LTR instruction).

7.2.1 

Task-State Segment (TSS)

The processor state information needed to restore a task is saved in a system segment called the task-state 
segment (TSS). Figure 7-2 shows the format of a TSS for tasks designed for 32-bit CPUs. The fields of a TSS are 
divided into two main categories: dynamic fields and static fields.
For information about 16-bit Intel 286 processor task structures, see Section 7.6, “16-Bit Task-State Segment 
(TSS).” For information about 64-bit mode task structures, see Section 7.7, “Task Management in 64-bit Mode.”