Vol. 3C 28-15
VMX SUPPORT FOR ADDRESS TRANSLATION
The following items detail the use of the various mappings:
•
If EPT is not in use (e.g., when outside VMX non-root operation), a logical processor may use cached mappings
as follows:
— For accesses using linear addresses, it may use linear mappings associated with the current VPID and the
current PCID. It may also use global TLB entries (linear mappings) associated with the current VPID and
any PCID.
— No guest-physical or combined mappings are used while EPT is not in use.
•
If EPT is in use, a logical processor may use cached mappings as follows:
— For accesses using linear addresses, it may use combined mappings associated with the current VPID, the
current PCID, and the current EP4TA. It may also use global TLB entries (combined mappings) associated
with the current VPID, the current EP4TA, and any PCID.
— For accesses using guest-physical addresses, it may use guest-physical mappings associated with the
current EP4TA.
— No linear mappings are used while EPT is in use.
28.3.3
Invalidating Cached Translation Information
Software modifications of paging structures (including EPT paging structures) may result in inconsistencies
between those structures and the mappings cached by a logical processor. Certain operations invalidate informa-
tion cached by a logical processor and can be used to eliminate such inconsistencies.
28.3.3.1 Operations that Invalidate Cached Mappings
The following operations invalidate cached mappings as indicated:
•
Operations that architecturally invalidate entries in the TLBs or paging-structure caches independent of VMX
operation (e.g., the INVLPG and INVPCID instructions) invalidate linear mappings and combined mappings.
1
They are required to do so only for the current VPID (but, for combined mappings, all EP4TAs). Linear
mappings for the current VPID are invalidated even if EPT is in use.
2
Combined mappings for the current
VPID are invalidated even if EPT is not in use.
3
•
An EPT violation invalidates any guest-physical mappings (associated with the current EP4TA) that would be
used to translate the guest-physical address that caused the EPT violation. If that guest-physical address was
the translation of a linear address, the EPT violation also invalidates any combined mappings for that linear
address associated with the current PCID, the current VPID and the current EP4TA.
•
If the “enable VPID” VM-execution control is 0, VM entries and VM exits invalidate linear mappings and
combined mappings associated with VPID 0000H (for all PCIDs). Combined mappings for VPID 0000H are
invalidated for all EP4TAs.
•
Execution of the INVVPID instruction invalidates linear mappings and combined mappings. Invalidation is
based on instruction operands, called the INVVPID type and the INVVPID descriptor. Four INVVPID types are
currently defined:
— Individual-address. If the INVVPID type is 0, the logical processor invalidates linear mappings and
combined mappings associated with the VPID specified in the INVVPID descriptor and that would be used
to translate the linear address specified in of the INVVPID descriptor. Linear mappings and combined
mappings for that VPID and linear address are invalidated for all PCIDs and, for combined mappings, all
1. See Section 4.10.4, “Invalidation of TLBs and Paging-Structure Caches,” in the Intel® 64 and IA-32 Architectures Software Devel-
oper’s Manual, Volume 3A for an enumeration of operations that architecturally invalidate entries in the TLBs and paging-structure
caches independent of VMX operation.
2. While no linear mappings are created while EPT is in use, a logical processor may retain, while EPT is in use, linear mappings (for the
same VPID as the current one) there were created earlier, when EPT was not in use.
3. While no combined mappings are created while EPT is not in use, a logical processor may retain, while EPT is in not use, combined
mappings (for the same VPID as the current one) there were created earlier, when EPT was in use.