42-2 Vol. 3D

INTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE

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While executing inside an enclave (legacy instructions and enclave instructions permitted inside an enclave).

42.3.2 

Interactions of Intel® SGX Instructions with Segment, Operand, and Addressing 

Prefixes

All the memory operands used by the Intel SGX instructions are interpreted as offsets within the data segment 
(DS). The segment-override prefix on Intel SGX instructions is ignored.
Operand size is fixed for each enclave instruction. The operand-size prefix is reserved, and results in a #UD excep-
tion if used.
All address sizes are determined by the operating mode of the processor. The address-size prefix is ignored. This 
implies that while operating in 64-bit mode of operation, the address size is always 64 bits, and while operating in 
32-bit mode of operation, the address size is always 32 bits. Additionally, when operating in 16-bit addressing, 
memory operands used by enclave instructions use 32 bit addressing; the value of CS.D is ignored.

42.3.3 

Interaction of Intel® SGX Instructions with Segmentation

All leaf functions of ENCLU and ENCLS instructions require that the DS segment be usable, and be an expand-up 
segment. Failing this check results in generation of a #GP(0) exception.
The Intel SGX leaf functions used for entering the enclave (ENCLU[EENTER] and ENCLU[ERESUME]) operate as 
follows:

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All usable segment registers except for FS and GS have a zero base. 

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The contents of the FS/GS segment registers (including the hidden portion) is saved in the processor.

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New FS and GS values compatible with enclave security are loaded from the TCS

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The linear ranges and access rights available under the newly-loaded FS and GS must abide to OS policies by 
ensuring they are subsets of the linear-address range and access rights available for the DS segment.

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The CS segment mode (64-bit, compatible, or 32 bit modes) must be consistent with the segment mode for 
which the enclave was created, as indicated by the SECS.ATTRIBUTES.MODE64 bit, and that the CPL of the 
logical processor is 3

An exit from the enclave either via ENCLU[EEXIT] or via an AEX restores the saved values of FS/GS segment regis-
ters.

42.3.4 

Interactions of Enclave Execution with Segmentation

During the course of execution, enclave code abides by all segmentation policies as dictated by IA32 and Intel 64 
Architectures, and generates appropriate exceptions on violations.
Additionally, any attempt by software executing inside an enclave to modify the processor's segmentation state 
(e.g. via MOV seg register, POP seg register, LDS, far jump, etc; excluding WRFSBASE/WRGSBASE) results in the 
generation of a #UD. See Section 39.6.1 for more information.
Upon enclave entry via the EENTER leaf function, FS is loaded from the (TCS.OFSBASE + SECS.BASEADDR) and 
TCS.FSLIMIT fields and GS is loaded from the (TCS.OGSBASE + SECS.BASEADDR) and TCS.GSLIMIT fields. 
Execution of WRFSBASE and WRGSBASE from inside a 64-bit enclave is allowed. The processor will save the new 
values into the current SSA frame on an asynchronous exit (AEX) and restore them back on enclave entry via 
ENCLU[ERESUME] instruction.

42.4 INTERACTIONS 

WITH 

PAGING

Intel SGX instructions are available only when the processor is executing in a protected mode of operation. Addi-
tionally, all Intel SGX leaf functions except for EDBGRD and EDBGWR are available only if paging is enabled. Any 
attempt to execute these leaf functions with paging disabled results in an invalid-opcode exception (#UD). As with