Vol. 3B 14-23

POWER AND THERMAL MANAGEMENT

In each chip-multiprocessing (CMP) silicon die, each core has a unique thermal sensor that triggers independently. 
These thermal sensor can trigger TM1 or TM2 transitions in the same manner as described in Section 14.7.2.1 and 
Section 14.7.2.2. The trip point of the thermal sensor is not programmable by software since it is set during the 
fabrication of the processor. 
Each thermal sensor in a processor core may be triggered independently to engage thermal management features. 
In Adaptive TM, both cores will transition to a lower frequency and/or lower voltage level if one sensor is triggered.
Triggering of this sensor is visible to software via the thermal interrupt LVT entry in the local APIC of a given core. 

14.7.3 

Software Controlled Clock Modulation

Pentium 4, Intel Xeon and Pentium M processors also support software-controlled clock modulation. This provides 
a means for operating systems to implement a power management policy to reduce the power consumption of the 
processor. Here, the stop-clock duty cycle is controlled by software through the IA32_CLOCK_MODULATION MSR 
(see Figure 14-25). 

The IA32_CLOCK_MODULATION MSR contains the following flag and field used to enable software-controlled clock 
modulation and to select the clock modulation duty cycle:

•

On-Demand Clock Modulation Enable, bit 4 — Enables on-demand software controlled clock modulation 
when set; disables software-controlled clock modulation when clear.

•

On-Demand Clock Modulation Duty Cycle, bits 1 through 3 — Selects the on-demand clock modulation 
duty cycle (see Table 14-3). This field is only active when the on-demand clock modulation enable flag is set.

Note that the on-demand clock modulation mechanism (like the thermal monitor) controls the processor’s stop-
clock circuitry internally to modulate the clock signal. The STPCLK# pin is not used in this mechanism.

The on-demand clock modulation mechanism can be used to control processor power consumption. Power 
management software can write to the IA32_CLOCK_MODULATION MSR to enable clock modulation and to select 
a modulation duty cycle. If on-demand clock modulation and TM1 are both enabled and the thermal status of the 
processor is hot (bit 0 of the IA32_THERM_STATUS MSR is set), clock modulation at the duty cycle specified by TM1 
takes precedence, regardless of the setting of the on-demand clock modulation duty cycle.

Figure 14-25.  IA32_CLOCK_MODULATION MSR

Table 14-3.  On-Demand Clock Modulation Duty Cycle Field Encoding

Duty Cycle Field Encoding

Duty Cycle

000B

Reserved

001B

12.5% (Default)

010B

25.0%

011B

37.5%

100B

50.0%

101B

63.5%

110B

75%

111B

87.5%

63

0

Reserved

1

3

On-Demand Clock Modulation Duty Cycle

On-Demand Clock Modulation Enable

4

5

Reserved