10-28 Vol. 3A

ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)

4. When interrupts are pending in the IRR register, the local APIC dispatches them to the processor one at a time, 

based on their priority and the current processor priority in the PPR (see Section 10.8.3.1, “Task and Processor 
Priorities”).

5. When a fixed interrupt has been dispatched to the processor core for handling, the completion of the handler 

routine is indicated with an instruction in the instruction handler code that writes to the end-of-interrupt (EOI) 
register in the local APIC (see Section 10.8.5, “Signaling Interrupt Servicing Completion”). The act of writing to 
the EOI register causes the local APIC to delete the interrupt from its queue and (for level-triggered interrupts) 
send a message on the bus indicating that the interrupt handling has been completed. (A write to the EOI 
register must not be included in the handler routine for an NMI, SMI, INIT, ExtINT, or SIPI.)

The following sections describe the acceptance of interrupts and their handling by the local APIC and processor in 
greater detail. 

10.8.3 

Interrupt, Task, and Processor Priority

Each interrupt delivered to the processor through the local APIC has a priority based on its vector number. The local 
APIC uses this priority to determine when to service the interrupt relative to the other activities of the processor, 
including the servicing of other interrupts. 
Each interrupt vector is an 8-bit value. The interrupt-priority class is the value of bits 7:4 of the interrupt vector. 
The lowest interrupt-priority class is 1 and the highest is 15; interrupts with vectors in the range 0–15 (with inter-
rupt-priority class 0) are illegal and are never delivered. Because vectors 0–31 are reserved for dedicated uses by 
the Intel 64 and IA-32 architectures, software should configure interrupt vectors to use interrupt-priority classes in 
the range 2–15.
Each interrupt-priority class encompasses 16 vectors. The relative priority of interrupts within an interrupt-priority 
class is determined by the value of bits 3:0 of the vector number. The higher the value of those bits, the higher the 
priority within that interrupt-priority class. Thus, each interrupt vector comprises two parts, with the high 4 bits 
indicating its interrupt-priority class and the low 4 bits indicating its ranking within the interrupt-priority class.

10.8.3.1   Task and Processor Priorities

The local APIC also defines a task priority and a processor priority that determine the order in which interrupts 
are handled. The task-priority class is the value of bits 7:4 of the task-priority register (TPR), which can be 
written by software (TPR is a read/write register); see Figure 10-18. 

NOTE

In this discussion, the term “task” refers to a software defined task, process, thread, program, or 
routine that is dispatched to run on the processor by the operating system. It does not refer to an 
IA-32 architecture defined task as described in Chapter 7, “Task Management.”

The task priority allows software to set a priority threshold for interrupting the processor. This mechanism enables 
the operating system to temporarily block low priority interrupts from disturbing high-priority work that the 
processor is doing. The ability to block such interrupts using task priority results from the way that the TPR controls 
the value of the processor-priority register (PPR).

5

 

Figure 10-18.  Task-Priority Register (TPR)

5. The TPR also determines the arbitration priority of the local processor; see Section 10.6.2.4, “Lowest Priority Delivery Mode.”

31

0

7

8

Reserved

Address: FEE0 0080H
Value after reset: 0H

Task-Priority Sub-Class

Task-Priority Class

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