17-60 Vol. 3B
DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
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Accessing a QOS mask register outside the supported COS (the max COS number is specified in
CPUID.(EAX=10H, ECX=ResID):EDX[15:0]), or
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Writing a COS greater than the supported maximum (specified as the maximum value of CPUID.(EAX=10H,
ECX=ResID):EDX[15:0] for all valid ResID values) is written to the IA32_PQR_ASSOC.CLOS field.
When CDP is enabled, specifying a COS value in IA32_PQR_ASSOC.COS outside of the lower half of the COS space
will cause undefined performance impact to code and data fetches due to MSR space re-indexing into code/data
masks when CDP is enabled.
When reading the IA32_PQR_ASSOC register the currently programmed COS on the core will be returned.
When reading an IA32_resourceType_MASK_n register the current capacity bit mask for COS 'n' will be returned.
As noted previously, software should minimize migrations of COS across logical processors (across threads or
cores), as a reduction in the accuracy of the Cache Allocation feature may result if COS are migrated frequently.
This is aligned with the industry standard practice of minimizing unnecessary thread migrations across processor
cores in order to avoid excessive time spent warming up processor caches after a migration. In general, for best
performance, minimize thread migration and COS migration across processor logical threads and processor cores.
17.17.5.2 Cache Allocation Technology Operation With Power Saving Features
Note that the Cache Allocation Technology feature cannot be used to enforce cache coherency, and that some
advanced power management features such as C-states which may shrink or power off various caches within the
system may interfere with CAT hints - in such cases the CAT bitmasks are ignored and the other features take
precedence. If the highest possible level of CAT differentiation or determinism is required, disable any power-
saving features which shrink the caches or power off caches. The details of the power management interfaces are
typically implementation-specific, but can be found at Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3C.
If software requires differentiation between threads but not absolute determinism then in many cases it is possible
to leave power-saving cache shrink features enabled, which can provide substantial power savings and increase
battery life in mobile platforms. In such cases when the caches are powered off (e.g., package C-states) the entire
cache of a portion thereof may be powered off. Upon resuming an active state any new incoming data to the cache
will be filled subject to the cache capacity bitmasks. Any data in the cache prior to the cache shrink or power off
may have been flushed to memory during the process of entering the idle state, however, and is not guaranteed to
remain in the cache. If differentiation between threads is the goal of system software then this model allows
substantial power savings while continuing to deliver performance differentiation. If system software needs
optimal determinism then power saving modes which flush portions of the caches and power them off should be
disabled.
NOTE
IA32_PQR_ASSOC is saved and restored across C6 entry/exit. Similarly, the mask register contents
are saved across package C-state entry/exit and are not lost.
17.17.5.3 Cache Allocation Technology Operation with Other Operating Modes
The states in IA32_PQR_ASSOC and mask registers are unmodified across an SMI delivery. Thus, the execution of
SMM handler code can interact with the Cache Allocation Technology resource and manifest some degree of non-
determinism to the non-SMM software stack. An SMM handler may also perform certain system-level or power
management practices that affect CAT operation.
It is possible for an SMM handler to minimize the impact on data determinism in the cache by reserving a COS with
a dedicated partition in the cache. Such an SMM handler can switch to the dedicated COS immediately upon
entering SMM, and switching back to the previously running COS upon exit.