Vol. 3C 36-9

INTEL® PROCESSOR TRACE

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Configured to go to an MMIO debug port, in order to route Intel PT output to a platform-specific trace endpoint 
(e.g., JTAG). In this scenario, a specific range of addresses is written in a circular manner, and SoC will 
intercept these writes and direct them to the proper device. Repeated writes to the same address do not 
overwrite each other, but are accumulated by the debugger, and hence no data is lost by the circular nature of 
the buffer. 

The processor will determine the address to which to write the next trace packet output byte as follows:

OutputBase[63:0] 

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 IA32_RTIT_OUTPUT_BASE[63:0]

OutputMask[63:0] 

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 ZeroExtend64(IA32_RTIT_OUTPUT_MASK_PTRS[31:0])

OutputOffset[63:0] 

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 ZeroExtend64(IA32_RTIT_OUTPUT_MASK_PTRS[63:32])

trace_store_phys_addr

 



 (OutputBase & ~OutputMask) + (OutputOffset & OutputMask)

Single-Range Output Errors

If the output base and mask are not properly configured by software, an operational error (see Section 36.3.9) will 
be signaled, and tracing disabled. Error scenarios with single-range output are:

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Mask value is non-contiguous.
IA32_RTIT_OUTPUT_MASK_PTRS.MaskOrTablePointer value has a 0 in a less significant bit position than the
most significant bit containing a 1.

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Base address and Mask are mis-aligned, and have overlapping bits set.
IA32_RTIT_OUTPUT_BASE && IA32_RTIT_OUTPUT_MASK_PTRS.MaskOrTableOffset > 0. 

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Illegal Output Offset
IA32_RTIT_OUTPUT_MASK_PTRS.OutputOffset is greater than the mask value
(IA32_RTIT_OUTPUT_MASK_PTRS.MaskOrTableOffset).

Also note that errors can be signaled due to trace packet output overlapping with restricted memory, see Section 
36.2.6.4.

36.2.6.2   Table of Physical Addresses (ToPA)

When IA32_RTIT_CTL.ToPA is set and IA32_RTIT_CTL.FabricEn is clear, the ToPA output mechanism is utilized. The 
ToPA mechanism uses a linked list of tables; see Figure 36-1 for an illustrative example. Each entry in the table 
contains some attribute bits, a pointer to an output region, and the size of the region. The last entry in the table 
may hold a pointer to the next table. This pointer can either point to the top of the current table (for circular array) 
or to the base of another table. The table size is not fixed, since the link to the next table can exist at any entry.
The processor treats the various output regions referenced by the ToPA table(s) as a unified buffer. This means that 
a single packet may span the boundary between one output region and the next.
The ToPA mechanism is controlled by three values maintained by the processor:

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proc_trace_table_base.
This is the physical address of the base of the current ToPA table. When tracing is enabled, the processor loads 
this value from the IA32_RTIT_OUTPUT_BASE MSR. While tracing is enabled, the processor updates the 
IA32_RTIT_OUTPUT_BASE MSR with changes to proc_trace_table_base, but these updates may not be 
synchronous to software execution. When tracing is disabled, the processor ensures that the MSR contains the 
latest value of proc_trace_table_base.

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proc_trace_table_offset.
This indicates the entry of the current table that is currently in use. (This entry contains the address of the 
current output region.) When tracing is enabled, the processor loads this value from bits 31:7 (MaskOrT-
ableOffset) of the IA32_RTIT_OUTPUT_MASK_PTRS. While tracing is enabled, the processor updates 
IA32_RTIT_OUTPUT_MASK_PTRS.MaskOrTableOffset with changes to proc_trace_table_offset, but these 
updates may not be synchronous to software execution. When tracing is disabled, the processor ensures that 
the MSR contains the latest value of proc_trace_table_offset.

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proc_trace_output_offset.
This a pointer into the current output region and indicates the location of the next write. When tracing is 
enabled, the processor loads this value from bits 63:32 (OutputOffset) of the