Vol. 3C 26-11

VM ENTRIES

— Bits 11:8 (reserved). If the register is CS or if the register is usable, these bits must all be 0.
— Bit 14 (D/B). For CS, D/B must be 0 if the guest will be IA-32e mode and the L bit (bit 13) in the

access-rights field is 1.

— Bit 15 (G). The following checks apply if the register is CS or if the register is usable:

•

If any bit in the limit field in the range 11:0 is 0, G must be 0.

•

If any bit in the limit field in the range 31:20 is 1, G must be 1.

— Bits 31:17 (reserved). If the register is CS or if the register is usable, these bits must all be 0.

— TR. The different sub-fields are considered separately:

•

Bits 3:0 (Type).
— If the guest will not be IA-32e mode, the Type must be 3 (16-bit busy TSS) or 11 (32-bit busy

TSS).

— If the guest will be IA-32e mode, the Type must be 11 (64-bit busy TSS).

•

Bit 4 (S). S must be 0.

•

Bit 7 (P). P must be 1.

•

Bits 11:8 (reserved). These bits must all be 0.

•

Bit 15 (G).
— If any bit in the limit field in the range 11:0 is 0, G must be 0.
— If any bit in the limit field in the range 31:20 is 1, G must be 1.

•

Bit 16 (Unusable). The unusable bit must be 0.

•

Bits 31:17 (reserved). These bits must all be 0.

— LDTR. The following checks on the different sub-fields apply only if LDTR is usable:

•

Bits 3:0 (Type). The Type must be 2 (LDT).

•

Bit 4 (S). S must be 0.

•

Bit 7 (P). P must be 1.

•

Bits 11:8 (reserved). These bits must all be 0.

•

Bit 15 (G).
— If any bit in the limit field in the range 11:0 is 0, G must be 0.
— If any bit in the limit field in the range 31:20 is 1, G must be 1.

•

Bits 31:17 (reserved). These bits must all be 0.

26.3.1.3   Checks on Guest Descriptor-Table Registers

The following checks are performed on the fields for GDTR and IDTR:

•

On processors that support Intel 64 architecture, the base-address fields must contain canonical addresses.

•

Bits 31:16 of each limit field must be 0.

26.3.1.4   Checks on Guest RIP and RFLAGS

The following checks are performed on fields in the guest-state area corresponding to RIP and RFLAGS:

•

RIP. The following checks are performed on processors that support Intel 64 architecture:
— Bits 63:32 must be 0 if the “IA-32e mode guest” VM-entry control is 0 or if the L bit (bit 13) in the access-

rights field for CS is 0.

— If the processor supports N < 64 linear-address bits, bits 63:N must be identical if the “IA-32e mode guest” 

VM-entry control is 1 and the L bit in the access-rights field for CS is 1.

1

 (No check applies if the processor 

supports 64 linear-address bits.)