20-4 Vol. 3B

8086 EMULATION

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LOCK prefix.

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Repeat prefixes REP, REPE, REPZ, REPNE, and REPNZ.

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Processor halt (HLT) instruction.

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No operation (NOP) instruction.

The following instructions, added to later IA-32 processors (some in the Intel 286 processor and the remainder in 
the Intel386 processor), can be executed in real-address mode, if backwards compatibility to the Intel 8086 
processor is not required.

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Move (MOV) instructions that operate on the control and debug registers.

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Load segment register instructions LSS, LFS, and LGS.

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Generalized multiply instructions and multiply immediate data.

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Shift and rotate by immediate counts.

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Stack instructions PUSHA, PUSHAD, POPA and POPAD, and PUSH immediate data.

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Move with sign extension instructions MOVSX and MOVZX.

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Long-displacement Jcc instructions.

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Exchange instructions CMPXCHG, CMPXCHG8B, and XADD. 

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String instructions MOVS, CMPS, SCAS, LODS, and STOS. 

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Bit test and bit scan instructions BT, BTS, BTR, BTC, BSF, and BSR; the byte-set-on condition instruction SETcc; 
and the byte swap (BSWAP) instruction.

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Double shift instructions SHLD and SHRD.

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EFLAGS control instructions PUSHF and POPF.

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ENTER and LEAVE control instructions.

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BOUND instruction.

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CPU identification (CPUID) instruction.

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System instructions CLTS, INVD, WINVD, INVLPG, LGDT, SGDT, LIDT, SIDT, LMSW, SMSW, RDMSR, WRMSR, 
RDTSC, and RDPMC.

Execution of any of the other IA-32 architecture instructions (not given in the previous two lists) in real-address 
mode result in an invalid-opcode exception (#UD) being generated.

20.1.4 

Interrupt and Exception Handling

When operating in real-address mode, software must provide interrupt and exception-handling facilities that are 
separate from those provided in protected mode. Even during the early stages of processor initialization when the 
processor is still in real-address mode, elementary real-address mode interrupt and exception-handling facilities 
must be provided to insure reliable operation of the processor, or the initialization code must insure that no inter-
rupts or exceptions will occur.
The IA-32 processors handle interrupts and exceptions in real-address mode similar to the way they handle them 
in protected mode. When a processor receives an interrupt or generates an exception, it uses the vector number of 
the interrupt or exception as an index into the interrupt table. (In protected mode, the interrupt table is called the 
interrupt descriptor table (IDT), but in real-address mode, the table is usually called the interrupt vector 
table, or simply the interrupt table.) The entry in the interrupt vector table provides a pointer to an interrupt- or 
exception-handler procedure. (The pointer consists of a segment selector for a code segment and a 16-bit offset 
into the segment.) The processor performs the following actions to make an implicit call to the selected handler:
1. Pushes the current values of the CS and EIP registers onto the stack. (Only the 16 least-significant bits of the 

EIP register are pushed.)

2. Pushes the low-order 16 bits of the EFLAGS register onto the stack.
3. Clears the IF flag in the EFLAGS register to disable interrupts.
4. Clears the TF, RF, and AC flags, in the EFLAGS register.