36-30 Vol. 3C

INTEL® PROCESSOR TRACE

36.3.2.2   Disabling Packet Generation

After disabling packet generation by clearing IA32_RTIT_CTL, it is advisable to read the IA32_RTIT_STATUS MSR 
(Section 36.2.7.4):

•

If the Error bit is set, an operational error was encountered, and the trace is most likely compromised. Software 
should check the source of the error (by examining the output MSR values), correct the source of the problem, 
and then attempt to gather the trace again. For details on operational errors, see Section 36.3.9. Software 
should clear IA32_RTIT_STATUS.Error before re-enabling packet generation. 

•

If the Stopped bit is set, software execution encountered an IP TraceStop (see Section 36.2.4.3) or the ToPA 
Stop condition (see “ToPA STOP” in Section 36.2.6.2) before packet generation was disabled.

36.3.3 

Flushing Trace Output

Packets are first buffered internally and then written out asynchronously. To collect packet output for post-
processing, a collector needs first to ensure that all packet data has been flushed from internal buffers. Software 
can ensure this by stopping packet generation by clearing IA32_RTIT_CTL.TraceEn (see “Disabling Packet Genera-
tion” in Section 36.2.7.2).
When software clears IA32_RTIT_CTL.TraceEn to flush out internally buffered packets, the logical processor issues 
an SFENCE operation which ensures that WC trace output stores will be ordered with respect to the next store, or 
serializing operation. A subsequent read from the same logical processor will see the flushed trace data, while a 
read from another logical processor should be preceded by a store, fence, or architecturally serializing operation on 
the tracing logical processor.
When the flush operations complete, the IA32_RTIT_OUTPUT_* MSR values indicate where the trace ended. While 
TraceEn is set, these MSRs may hold stale values.

36.3.4 Warm 

Reset

The MSRs software uses to program Intel Processor Trace are cleared after a power-on RESET (or cold RESET). On 
a warm RESET, the contents of those MSRs can retain their values from before the warm RESET with the exception 
that IA32_RTIT_CTL.TraceEn will be cleared (which may have the side effect of clearing some bits in 
IA32_RTIT_STATUS). 

36.3.5 

Context Switch Consideration

To facilitate construction of instruction execution traces at the granularity of a software process or thread context, 
software can save and restore the states of the trace configuration MSRs across the process or thread context 
switch boundary. The principle is the same as saving and restoring the typical architectural processor states across 
context switches. 

36.3.5.1   Manual Trace Configuration Context Switch

The configuration can be saved and restored through a sequence of instructions of RDMSR, management of MSR 
content and WRMSR. To stop tracing and to ensure that all configuration MSRs contain stable values, software must 
clear IA32_RTIT_CTL.TraceEn before reading any other trace configuration MSRs. The recommended method for 
saving trace configuration context manually follows:
1. RDMSR IA32_RTIT_CTL, save value to memory 
2. WRMSR IA32_RTIT_CTL with saved value from RDMSR above and TraceEn cleared
3. RDMSR all other configuration MSRs whose values had changed from previous saved value, save changed 

values to memory