Vol. 3A 6-23

INTERRUPT AND EXCEPTION HANDLING

Interrupt 3—Breakpoint Exception (#BP)

Exception Class

Trap.

Description

Indicates that a breakpoint instruction (INT 3, opcode CCH) was executed, causing a breakpoint trap to be gener-
ated. Typically, a debugger sets a breakpoint by replacing the first opcode byte of an instruction with the opcode 
for the INT 3 instruction. (The INT 3 instruction is one byte long, which makes it easy to replace an opcode in a 
code segment in RAM with the breakpoint opcode.) The operating system or a debugging tool can use a data 
segment mapped to the same physical address space as the code segment to place an INT 3 instruction in places 
where it is desired to call the debugger.
With the P6 family, Pentium, Intel486, and Intel386 processors, it is more convenient to set breakpoints with the 
debug registers. (See Section 17.3.2, “Breakpoint Exception (#BP)—Interrupt Vector 3,” for information about the 
breakpoint exception.) If more breakpoints are needed beyond what the debug registers allow, the INT 3 instruc-
tion can be used.
Any breakpoint exception inside an RTM region causes a transactional abort and, by default, redirects control flow 
to the fallback instruction address. If advanced debugging of RTM transactional regions has been enabled, any 
transactional abort due to a break exception instead causes execution to roll back to just before the XBEGIN 
instruction and then delivers a debug exception (#DB) — not a breakpoint exception. See Section 16.3.7, “RTM-
Enabled Debugger Support,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
A breakpoint exception can also be generated by executing the INT n instruction with an operand of 3. The action 
of this instruction (INT 3) is slightly different than that of the INT 3 instruction (see “INTn/INTO/INT3—Call to 
Interrupt Procedure” in Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 
2A).

Exception Error Code

None.

Saved Instruction Pointer

Saved contents of CS and EIP registers point to the instruction following the INT 3 instruction.

Program State Change

Even though the EIP points to the instruction following the breakpoint instruction, the state of the program is 
essentially unchanged because the INT 3 instruction does not affect any register or memory locations. The 
debugger can thus resume the suspended program by replacing the INT 3 instruction that caused the breakpoint 
with the original opcode and decrementing the saved contents of the EIP register. Upon returning from the 
debugger, program execution resumes with the replaced instruction.