10-40 Vol. 3A

ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)

x2APIC IDs in some clusters to provide for unique and non-overlapping system wide IDs before configuring the 
disconnected components into a single system. 

10.12.2  x2APIC Register Availability

The local APIC registers can be accessed via the MSR interface only when the local APIC has been switched to the 
x2APIC mode as described in Section 10.12.1. Accessing any APIC register in the MSR address range 0800H 
through 0BFFH via RDMSR or WRMSR when the local APIC is not in x2APIC mode causes a general-protection 
exception. In x2APIC mode, the memory mapped interface is not available and any access to the MMIO interface 
will behave similar to that of a legacy xAPIC in globally disabled state. Table 10-7 provides the interactions between 
the legacy & extended modes and the legacy and register interfaces.

10.12.3  MSR Access in x2APIC Mode

To allow for efficient access to the APIC registers in x2APIC mode, the serializing semantics of WRMSR are relaxed 
when writing to the APIC registers. Thus, system software should not use “WRMSR to APIC registers in x2APIC 
mode” as a serializing instruction. Read and write accesses to the APIC registers will occur in program order. A 
WRMSR to an APIC register may complete before all preceding stores are globally visible; software can prevent this 
by inserting a serializing instruction, an SFENCE, or an MFENCE before the WRMSR.
The RDMSR instruction is not serializing and this behavior is unchanged when reading APIC registers in x2APIC 
mode. System software accessing the APIC registers using the RDMSR instruction should not expect a serializing 
behavior. (Note: The MMIO-based xAPIC interface is mapped by system software as an un-cached region. Conse-
quently, read/writes to the xAPIC-MMIO interface have serializing semantics in the xAPIC mode.)

10.12.4  VM-Exit Controls for MSRs and x2APIC Registers

The VMX architecture allows a VMM to specify lists of MSRs to be loaded or stored on VMX transitions using the 
VMX-transition MSR areas (see VM-exit MSR-store address field, VM-exit MSR-load address field, and VM-entry 
MSR-load address field in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C).
The X2APIC MSRs cannot to be loaded and stored on VMX transitions. A VMX transition fails if the VMM has specified 
that the transition should access any MSRs in the address range from 0000_0800H to 0000_08FFH (the range used 
for accessing the X2APIC registers). Specifically, processing of an 128-bit entry in any of the VMX-transition MSR 
areas fails if bits 31:0 of that entry (represented as ENTRY_LOW_DW) satisfies the expression: “ENTRY_LOW_DW 
& FFFFF800H = 00000800H”. Such a failure causes an associated VM entry to fail (by reloading host state) and 
causes an associated VM exit to lead to VMX abort.

10.12.5  x2APIC State Transitions

This section provides a detailed description of the x2APIC states of a local x2APIC unit, transitions between these 
states as well as interactions of these states with INIT and reset. 

10.12.5.1   x2APIC States

The valid states for a local x2APIC unit is listed in Table 10-5:

•

APIC disabled: IA32_APIC_BASE[EN]=0 and IA32_APIC_BASE[EXTD]=0

•

xAPIC mode: IA32_APIC_BASE[EN]=1 and IA32_APIC_BASE[EXTD]=0

Table 10-7. MSR/MMIO Interface of a Local x2APIC in Different Modes of Operation

MMIO Interface

MSR Interface

xAPIC mode

Available

General-protection exception

x2APIC mode

Behavior identical to xAPIC in globally disabled state

Available