Vol. 3C 30-3

VMX INSTRUCTION REFERENCE

INVEPT— Invalidate Translations Derived from EPT

Description

Invalidates mappings in the translation lookaside buffers (TLBs) and paging-structure caches that were derived 
from extended page tables (EPT). (See Chapter 28, “VMX Support for Address Translation”.) Invalidation is based 
on the INVEPT type specified in the register operand and the INVEPT descriptor specified in the memory 
operand.
Outside IA-32e mode, the register operand is always 32 bits, regardless of the value of CS.D; in 64-bit mode, the 
register operand has 64 bits (the instruction cannot be executed in compatibility mode).
The INVEPT types supported by a logical processors are reported in the IA32_VMX_EPT_VPID_CAP MSR (see 
Appendix A, “VMX Capability Reporting Facility”). There are two INVEPT types currently defined:

•

Single-context invalidation. If the INVEPT type is 1, the logical processor invalidates all mappings associated 
with bits 51:12 of the EPT pointer (EPTP) specified in the INVEPT descriptor. It may invalidate other mappings 
as well.

•

Global invalidation: If the INVEPT type is 2, the logical processor invalidates mappings associated with all 
EPTPs.

If an unsupported INVEPT type is specified, the instruction fails.
INVEPT invalidates all the specified mappings for the indicated EPTP(s) regardless of the VPID and PCID values with 
which those mappings may be associated.
The INVEPT descriptor comprises 128 bits and contains a 64-bit EPTP value in bits 63:0 (see Figure 30-1).

Operation

IF (not in VMX operation) or (CR0.PE = 0) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)

THEN #UD;

ELSIF in VMX non-root operation

THEN VM exit;

ELSIF CPL

>

 0

THEN #GP(0);
ELSE

INVEPT_TYPE ← value of register operand;

IF IA32_VMX_EPT_VPID_CAP MSR indicates that processor does not support INVEPT_TYPE

THEN VMfail(Invalid operand to INVEPT/INVVPID);
ELSE

// INVEPT_TYPE must be 1 or 2

INVEPT_DESC ← value of memory operand;

EPTP ← INVEPT_DESC[63:0];

Opcode

Instruction

Description

66 0F 38 80

INVEPT r64, m128

Invalidates EPT-derived entries in the TLBs and paging-structure caches (in 64-

bit mode)

66 0F 38 80

INVEPT r32, m128

Invalidates EPT-derived entries in the TLBs and paging-structure caches (outside 

64-bit mode)

Figure 30-1.  INVEPT Descriptor

127

64 63

0

Reserved (must be zero)

EPT pointer (EPTP)