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Vol. 3A 6-7

INTERRUPT AND EXCEPTION HANDLING

The fact that the group of maskable hardware interrupts includes the reserved interrupt and exception vectors 0 
through 32 can potentially cause confusion. Architecturally, when the IF flag is set, an interrupt for any of the 
vectors from 0 through 32 can be delivered to the processor through the INTR pin and any of the vectors from 16 
through 32 can be delivered through the local APIC. The processor will then generate an interrupt and call the 
interrupt or exception handler pointed to by the vector number. So for example, it is possible to invoke the page-
fault handler through the INTR pin (by means of vector 14); however, this is not a true page-fault exception. It is 
an interrupt. As with the INT n instruction (see Section 6.4.2, “Software-Generated Exceptions”), when an inter-
rupt is generated through the INTR pin to an exception vector, the processor does not push an error code on the 
stack, so the exception handler may not operate correctly.
The IF flag can be set or cleared with the STI (set interrupt-enable flag) and CLI (clear interrupt-enable flag) 
instructions, respectively. These instructions may be executed only if the CPL is equal to or less than the IOPL. A 
general-protection exception (#GP) is generated if they are executed when the CPL is greater than the IOPL. (The 
effect of the IOPL on these instructions is modified slightly when the virtual mode extension is enabled by setting 
the VME flag in control register CR4: see Section 20.3, “Interrupt and Exception Handling in Virtual-8086 Mode.” 
Behavior is also impacted by the PVI flag: see Section 20.4, “Protected-Mode Virtual Interrupts.”
The IF flag is also affected by the following operations:

The PUSHF instruction stores all flags on the stack, where they can be examined and modified. The POPF 
instruction can be used to load the modified flags back into the EFLAGS register.

Task switches and the POPF and IRET instructions load the EFLAGS register; therefore, they can be used to 
modify the setting of the IF flag.

When an interrupt is handled through an interrupt gate, the IF flag is automatically cleared, which disables 
maskable hardware interrupts. (If an interrupt is handled through a trap gate, the IF flag is not cleared.)

See the descriptions of the CLI, STI, PUSHF, POPF, and IRET instructions in Chapter 3, “Instruction Set Reference, 
A-L,”
 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, and Chapter 4, “Instruc-
tion Set Reference, M-U,” in th
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B, for 
detailed description of the operations these instructions are allowed to perform on the IF flag.

6.8.2 

Masking Instruction Breakpoints

The RF (resume) flag in the EFLAGS register controls the response of the processor to instruction-breakpoint condi-
tions (see the description of the RF flag in Section 2.3, “System Flags and Fields in the EFLAGS Register”). 
When set, it prevents an instruction breakpoint from generating a debug exception (#DB); when clear, instruction 
breakpoints will generate debug exceptions. The primary function of the RF flag is to prevent the processor from 
going into a debug exception loop on an instruction-breakpoint. See Section 17.3.1.1, “Instruction-Breakpoint 
Exception Condition,” for more 
information on the use of this flag.

6.8.3 

Masking Exceptions and Interrupts When Switching Stacks

To switch to a different stack segment, software often uses a pair of instructions, for example:

MOV SS, AX
MOV ESP, StackTop

If an interrupt or exception occurs after the segment selector has been loaded into the SS register but before the 
ESP register has been loaded, these two parts of the logical address into the stack space are inconsistent for the 
duration of the interrupt or exception handler.
To prevent this situation, the processor inhibits interrupts, debug exceptions, and single-step trap exceptions after 
either a MOV to SS instruction or a POP to SS instruction, until the instruction boundary following the next instruc-
tion is reached. All other faults may still be generated. If the LSS instruction is used to modify the contents of the 
SS register (which is the recommended method of modifying this register), this problem does not occur.