10-4 Vol. 3A

ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)

10.2 

SYSTEM BUS VS. APIC BUS

For the P6 family and Pentium processors, the I/O APIC and local APICs communicate through the 3-wire inter-
APIC bus (see Figure 10-3). Local APICs also use the APIC bus to send and receive IPIs. The APIC bus and its 
messages are invisible to software and are not classed as architectural.
Beginning with the Pentium 4 and Intel Xeon processors, the I/O APIC and local APICs (using the xAPIC architec-
ture) communicate through the system bus (see Figure 10-2). The I/O APIC sends interrupt requests to the 
processors on the system bus through bridge hardware that is part of the Intel chip set. The bridge hardware 
generates the interrupt messages that go to the local APICs. IPIs between local APICs are transmitted directly on 
the system bus.

10.3 THE 

INTEL

®

 82489DX EXTERNAL APIC, THE APIC, THE XAPIC, AND THE 

X2APIC

The local APIC in the P6 family and Pentium processors is an architectural subset of the Intel

®

 82489DX external 

APIC. See Section 22.27.1, “Software Visible Differences Between the Local APIC and the 82489DX.”
The APIC architecture used in the Pentium 4 and Intel Xeon processors (called the xAPIC architecture) is an exten-
sion of the APIC architecture found in the P6 family processors. The primary difference between the APIC and 
xAPIC architectures is that with the xAPIC architecture, the local APICs and the I/O APIC communicate through the 
system bus. With the APIC architecture, they communication through the APIC bus (see Section 10.2, “System Bus 
Vs. APIC Bus”). Also, some APIC architectural features have been extended and/or modified in the xAPIC architec-
ture. These extensions and modifications are described in Section 10.4 through Section 10.10.
The basic operating mode of the xAPIC is xAPIC mode. The x2APIC architecture is an extension of the xAPIC 
architecture, primarily to increase processor addressability. The x2APIC architecture provides backward compati-
bility to the xAPIC architecture and forward extendability for future Intel platform innovations. These extensions 
and modifications are supported by a new mode of execution (x2APIC mode) are detailed in Section 10.12.

10.4 LOCAL 

APIC

The following sections describe the architecture of the local APIC and how to detect it, identify it, and determine its 
status. Descriptions of how to program the local APIC are given in Section 10.5.1, “Local Vector Table,” and Section 
10.6.1, “Interrupt Command Register (ICR).”

10.4.1 

The Local APIC Block Diagram

Figure 10-4 gives a functional block diagram for the local APIC. Software interacts with the local APIC by reading 
and writing its registers. APIC registers are memory-mapped to a 4-KByte region of the processor’s physical 
address space with an initial starting address of FEE00000H. For correct APIC operation, this address space must 
be mapped to an area of memory that has been designated as strong uncacheable (UC). See Section 11.3, 
“Methods of Caching Available.”
In MP system configurations, the APIC registers for Intel 64 or IA-32 processors on the system bus are initially 
mapped to the same 4-KByte region of the physical address space. Software has the option of changing initial 
mapping to a different 4-KByte region for all the local APICs or of mapping the APIC registers for each local APIC to 
its own 4-KByte region. Section 10.4.5, “Relocating the Local APIC Registers,” describes how to relocate the base 
address for APIC registers.
On processors supporting x2APIC architecture (indicated by CPUID.01H:ECX[21] = 1), the local APIC supports 
operation both in xAPIC mode and (if enabled by software) in x2APIC mode. x2APIC mode provides extended 
processor addressability (see Section 10.12).