17-42 Vol. 3B

DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES

logical processor, software seeking to synchronize the TSC values of multiple logical processors must perform these 
writes on each logical processor. It may be difficult for software to do this in a way than ensures that all logical 
processors will have the same value for the TSC at a given point in time.
The synchronization of TSC adjustment can be simplified by using the 64-bit IA32_TSC_ADJUST MSR (address 
3BH). Like the IA32_TIME_STAMP_COUNTER MSR, the IA32_TSC_ADJUST MSR is maintained separately for each 
logical processor. A logical processor maintains and uses the IA32_TSC_ADJUST MSR as follows:

•

On RESET, the value of the IA32_TSC_ADJUST MSR is 0.

•

If an execution of WRMSR to the IA32_TIME_STAMP_COUNTER MSR adds (or subtracts) value X from the TSC, 
the logical processor also adds (or subtracts) value X from the IA32_TSC_ADJUST MSR.

•

If an execution of WRMSR to the IA32_TSC_ADJUST MSR adds (or subtracts) value X from that MSR, the logical 
processor also adds (or subtracts) value X from the TSC.

Unlike the TSC, the value of the IA32_TSC_ADJUST MSR changes only in response to WRMSR (either to the MSR 
itself, or to the IA32_TIME_STAMP_COUNTER MSR). Its value does not otherwise change as time elapses. Software 
seeking to adjust the TSC can do so by using WRMSR to write the same value to the IA32_TSC_ADJUST MSR on 
each logical processor.
Processor support for the IA32_TSC_ADJUST MSR is indicated by CPUID.(EAX=07H, ECX=0H):EBX.TSC_ADJUST 
(bit 1).

17.15.4 Invariant 

Time-Keeping

The invariant TSC is based on the invariant timekeeping hardware (called Always Running Timer or ART), that runs 
at the core crystal clock frequency. The ratio defined by CPUID leaf 15H expresses the frequency relationship 
between the ART hardware and TSC.
If CPUID.15H:EBX[31:0] != 0 and CPUID.80000007H:EDX[InvariantTSC] = 1, the following linearity relationship 
holds between TSC and the ART hardware:

TSC_Value = (ART_Value * CPUID.15H:EBX[31:0] )/ CPUID.15H:EAX[31:0] + K

Where 'K' is an offset that can be adjusted by a privileged agent

2

.

When ART hardware is reset, both invariant TSC and K are also reset.

17.16  INTEL® RESOURCE DIRECTOR TECHNOLOGY (INTEL® RDT) MONITORING 

FEATURES

The Intel Resource Director Technology (Intel RDT) feature set provides a set of monitoring capabilities including 
Cache Monitoring Technology (CMT) and Memory Bandwidth Monitoring (MBM). The Intel

®

 Xeon

®

 processor E5 v3 

family introduced resource monitoring capability in each logical processor to measure specific platform shared 
resource metrics, for example, L3 cache occupancy. The programming interface for these monitoring features is 
described in this section. Two features within the monitoring feature set provided are described - Cache Monitoring 
Technology (CMT) and Memory Bandwidth Monitoring.
Cache Monitoring Technology (CMT) allows an Operating System, Hypervisor or similar system management agent 
to determine the usage of cache by applications running on the platform. The initial implementation is directed at 
L3 cache monitoring (currently the last level cache in most server platforms).   
Memory Bandwidth Monitoring (MBM), introduced in the Intel

®

 Xeon

®

 processor E5 v4 family, builds on the CMT 

infrastructure to allow monitoring of bandwidth from one level of the cache hierarchy to the next - in this case 
focusing on the L3 cache, which is typically backed directly by system memory. As a result of this implementation, 
memory bandwidth can be monitored.
The monitoring mechanisms described provide the following key shared infrastructure features:

2. IA32_TSC_ADJUST MSR and the TSC-offset field in the VM execution controls of VMCS are some of the common interfaces that priv-

ileged software can use to manage the time stamp counter for keeping time