Vol. 3B 17-49
DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
17.16.8.1 Monitoring Dynamic Configuration
Both the IA32_QM_EVTSEL and IA32_PQR_ASSOC registers are accessible and modifiable at any time during
execution using RDMSR/WRMSR unless otherwise noted. When writing to these MSRs a #GP(0) will be generated
if any of the following conditions occur:
•
A reserved bit is modified,
•
An RMID exceeding the maxRMID is used.
17.16.8.2 Monitoring Operation With Power Saving Features
Note that some advanced power management features such as deep package C-states may shrink the L3 cache
and cause CMT occupancy count to be reduced. MBM bandwidth counts may increase due to flushing cached data
out of L3.
17.16.8.3 Monitoring Operation with Other Operating Modes
The states in IA32_PQR_ASSOC and monitoring counter are unmodified across an SMI delivery. Thus, the execu-
tion of SMM handler code and SMM handler’s data can manifest as spurious contribution in the monitored data.
It is possible for an SMM handler to minimize the impact on of spurious contribution in the QOS monitoring coun-
ters by reserving a dedicated RMID for monitoring the SMM handler. Such an SMM handler can save the previously
configured QOS Monitoring state immediately upon entering SMM, and restoring the QOS monitoring state back to
the prev-SMM RMID upon exit.
17.16.8.4 Monitoring Operation with RAS Features
In general the Reliability, Availability and Serviceability (RAS) features present in Intel Platforms are not expected
to significantly affect shared resource monitoring counts. In cases where software RAS features cause memory
copies or cache accesses these may be tracked and may influence the shared resource monitoring counter values.
17.17 INTEL® RESOURCE DIRECTOR TECHNOLOGY (INTEL® RDT) ALLOCATION
FEATURES
The Intel Resource Director Technology (Intel RDT) feature set provides a set of allocation (resource control) capa-
bilities including Cache Allocation Technology (CAT) and Code and Data Prioritization (CDP). The Intel Xeon
processor E5 v4 family (and subset of communication-focused Intel Xeon processors E5 v3 family) introduce capa-
bilities to configure and make use of the Cache Allocation Technology (CAT) mechanisms on the L3 cache. Some
future Intel platforms may also provide support for control over the L2 cache, with capabilities as described below.
The programming interface for Cache Allocation Technology and for the more general allocation capabilities are
described in the rest of this chapter.
Cache Allocation Technology enables an Operating System (OS), Hypervisor /Virtual Machine Manager (VMM) or
similar system service management agent to specify the amount of cache space into which an application can fill
(as a hint to hardware - certain features such as power management may override CAT settings). Specialized user-
level implementations with minimal OS support are also possible, though not necessarily recommended (see notes
below for OS/Hypervisor with respect to ring 3 software and virtual guests). Depending on the processor famility,
L2 or L3 cache allocation capability may be provided, and the technology is designed to scale across multiple cache
levels and technology generations.
Software can determine which levels are supported in a give platform programmatically using CPUID as described
in the following sections.
The CAT mechanisms defined in this document provide the following key features:
•
A mechanism to enumerate platform Cache Allocation Technology capabilities and available resource types that
provides CAT control capabilities. For implementations that support Cache Allocation Technology, CPUID
provides enumeration support to query which levels of the cache hierarchy are supported and specific CAT
capabilities, such as the max allocation bitmask size,