Vol. 3C 36-79

INTEL® PROCESSOR TRACE

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Relinquish ownership of the trace configuration MSRs by clearing the “enabled bits” of those configuration 
MSRs.

36.8.3 Tracking 

Time 

This section describes the relationships of several clock counters whose update frequencies reside in different 
domains that feed into the timing packets. To track time, the decoder also needs to know the regularity or irregu-
larity of the occurrences of various timing packets that store those clock counters. 
Intel PT provides time information for three different but related domains:

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Processor timestamp counter
This counter increments at the max non-turbo or P1 frequency, and its value is returned on a RDTSC. Its

frequency is fixed. The TSC packet holds the lower 7 bytes of the timestamp counter value. The TSC packet

occurs occasionally and are much less frequent than the frequency of the time stamp counter. The timestamp

counter will continue to increment when the processor is in deep C-States, with the exception of processors

reporting CPUID.80000007H:EDX.InvariantTSC[bit 8] =0.

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Core crystal clock 
The ratio of the core crystal clock to timestamp counter frequency is known as P, and can calculating 
CPUID.15H:EBX[31:0] / CPUID.15H:EAX[31:0]. The frequency of the core crystal clock is fixed and lower than 
that of the timestamp counter. The periodic MTC packet is generated based on software-selected multiples of 
the crystal clock frequency. The MTC packet is expected to occur more frequently than the TSC packet.

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Processor core clock
The processor core clock frequency can vary due to P-state and thermal conditions. The CYC packet provides 
elapsed time as measured in processor core clock cycles relative to the last CYC packet. 

A decoder can use all or some combination of these packets to track time at different resolutions throughout the 
trace packets.

36.8.3.1   Time Domain Relationships

The three domains are related by the following formula:

TimeStampValue = (CoreCrystalClockValue * P) + AdjustedProcessorCycles + Software_Offset; 

The CoreCrystalClockValue can provide the coarse-grained component of the TSC value. P, or the TSC/”core crystal 
clock” ratio, can be derived from CPUID leaf 15H, as described in Section 36.8.3.
The AdjustedProcessorCycles component provides the fine-grained distance from the rising edge of the last core 
crystal clock. Specifically, it is a cycle count in the same frequency as the timestamp counter from the last crystal 
clock rising edge. The value is adjusted based on the ratio of the processor core clock frequency to the Maximum 
Non-Turbo (or P1) frequency. 
The Software_Offsets component includes software offsets that are factored into the timestamp value, such as 
IA32_TSC_ADJUST. 

36.8.3.2   Estimating TSC within Intel PT

For many usages, it may be useful to have an estimated timestamp value for all points in the trace. The formula 
provided in Section 36.8.3.1 above provides the framework for how such an estimate can be calculated from the 
various timing packets present in the trace.
The TSC packet provides the precise timestamp value at the time it is generated; however, TSC packets are infre-
quent, and estimates of the current timestamp value based purely on TSC packets are likely to be very inaccurate 
for this reason. In order to get more precise timing information between TSC packets, CYC packets and/or MTC 
packets should be enabled.
MTC packets provide incremental updates of the CoreCrystalClockValue. On processors that support CPUID leaf 
15H, the frequency of the timestamp counter and the core crystal clock is fixed, thus MTC packets provide a means 
to update the running timestamp estimate. Between two MTC packets A and B, the number of crystal clock cycles 
passed is calculated from the 8-bit payloads of respective MTC packets: